08-20-2019 05:48 PM
Below is the environment details.
Vivado = 2019.1, Board = Arty S7-50, objective=read image, perform few operations and then display the image. Approach, use CoE file -
1. convert the image and load it into BRAM, initialise as single port ROM.
2. read this initialized memory location, convert as matrix (for image processing)
3. perform operations like sobel, thresholding, etc, for which I have created IP using HLS which I plan to use in IP Integrator.
4. Display using Digilent PMOD
1. can someone validate this approach please?
2. can we achieve all of this using IP Integrator?
3. how do I prepare ROM contents so as to perform image processing actions?
4. Can someone help me with sequence please?
Pl. let me know what additional information I should furnish
08-22-2019 02:00 AM
You might want to read my Video Series 26: Examples of advanced uses of the AXI VDMA IP, example 3 is close from what you want to do for the reading from memory part.
Then you would have to change the memory from DDR to BRAM and initialise your BRAM from vivado using a coe file.
08-22-2019 04:01 AM
Thank you so much for your quick response, let me review the Video series as suggested by you, test and come back to you with my results or any additional questions, if any. Really appreciate your quick help.
09-23-2019 02:35 AM
Were you able to make you project working?
Thanks and Regards
09-27-2019 05:30 PM
My apologies for delay in response. Yes, I did look at your suggested videos and a big thank you for the same. As to the objective, I was hoping to do this without SDK route, came up with below design. I got an understanding that for VDMA to work I will have to take it through SDK only. Can you please take a critical view of the attached design? I have captured signals as well. Request your time and inputs as it will be a big help for me to move forward.
1. is the design heading in right direction? Any fundamental mistake that I am making here?
2. Clock freq = 74.5 (for 720p)
3. FID is held at 0
4. NO data from BRAM controller, Block Memory Generator is loading the COE
5. VTG_CE is low, no sync and blanking signals coming out of Timing Controller. Active Video though is high.
6. TREADY is high on both. but no data coming out.
7. I have two unconnected slaves - could those be causing the issue?
8. I have configured data interface as AXI and not AXI-Lite.
09-30-2019 01:51 AM
You have the underflow signal which is high, meaning that you have not enough data. You might want to check the TVALID signal coming to the AXI4-Stream to video out
Refer to Video Series 31 – Debugging a Video System using an ILA as well
10-03-2019 10:48 AM
10-04-2019 06:59 AM
I do not know what is the issue. Keep following my Video Series 31 – Debugging a Video System using an ILA . So if TVALID is low at the output of the FIFO then you check at its input to see if the issue is from the FIFO. Them with the next upstream IP...