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Observer oriany
Observer
240 Views
Registered: ‎11-02-2018

Regarding MIPI RX Clock Lane

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Hello,

 

I am designing a carrier board for a set of Xilinx Ultrascale+ SOMs to be used with MIPI cameras. The product guide for the MIPI CSI RX IP block specifies that clocks must be connected to DBC or QBC pins on the PS banks. However, across the SOMs I am working with, the positions of the DBC and QBC pins vary meaning that my carrier board loses pin compatibility depending on which SOM I am using. Is there some way for me to maintain pin compatibility other than multiplexing the MIPI clock lanes to the right DBC or QBC pins depending on the SOM plugged in?

 

Thanks,

Akhil

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Moderator
Moderator
186 Views
Registered: ‎11-09-2015

Re: Regarding MIPI RX Clock Lane

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Hi @oriany 

You should do a pin assignment for each configuration.Not only you will need to assign the clock lane to the correct DBC or QBC but you might need to change the lane assignment depending on your cloc, to make sure you placement is optimal.

I do not see how you can do differently

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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2 Replies
Moderator
Moderator
187 Views
Registered: ‎11-09-2015

Re: Regarding MIPI RX Clock Lane

Jump to solution

Hi @oriany 

You should do a pin assignment for each configuration.Not only you will need to assign the clock lane to the correct DBC or QBC but you might need to change the lane assignment depending on your cloc, to make sure you placement is optimal.

I do not see how you can do differently

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Observer oriany
Observer
124 Views
Registered: ‎11-02-2018

Re: Regarding MIPI RX Clock Lane

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Hi @florentw,

Thanks for the response. I thought it couldn't be done any other way either but just wanted to check.

 

Thanks

 

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