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Adventurer
Adventurer
232 Views
Registered: ‎07-29-2013

Register space of Video Processing Subsystem make me confused.

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I want to use Video Processing Subsystem  in my design to scale small video up to bigger. So I configured the IP with scale only mode.

After I read the PG231, I confused about the register describe sections.

Why the  Vertical scaler and  Horizontal scaler register in two sections?  

Some register address have different meanings.

For example. The register 0x020 means HwReg_HeightOut in Vertical scaler section, HwReg_WidthOut in Horizontal scaler section.

If I want to scale both vertical and Horizontal, like 1280*720 to 1920*1080. How could I do?

And I don't know how to calculate some register, like HwReg_LineRate, HwReg_PixelRate.

Some register could not know Where to find the enum value of it? like HwReg_ColorMode.

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Moderator
Moderator
156 Views
Registered: ‎11-09-2015

Re: Register space of Video Processing Subsystem make me confused.

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Hi @wbyjerry 

Aslo pleare refer to the note in the PG231 before the register space:

Note: Control of the video processing pipe is only supported through the Video Processing Subsystem driver. The register map is provided for debug purposes only.

You are expected to use the drivers to control the VPSS. This is the only supported flow.

So you shouldn't have to care about the actual value that have to be programmed in these registers. From a driver point of view, you just have to say what will be your input video format and what will be the output video format and the driver will take care of everything. Please refer to the examples mentioned by @ashokkum 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
167 Views
Registered: ‎04-09-2019

Re: Register space of Video Processing Subsystem make me confused.

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Hi @wbyjerry ,

Scaling is an operation of changing the video stream resolution. The scaling can be upscaling or downscaling. In the two cases VPSS is going to use different algorithems to calculate the mean value of the pixels and lines.

So, In horizontal scaling the new pixel will get create by calculating the mean value of the eachpixels which are adjusent to it. In vertical scaling, the newline will get create by calculating the meanvalue of the pixels in the above line and the below line to it. 

So, inverical scaling, To add the new lines, we are going to configure the 0x020 register which will adress about the new lines (active number of lines in a frame), that are expecting in the output to create the new resolution.

Similarly, line will be constructed with the array of pixels. So, in horizontal scaling the new pixels (active pixels number in a line) will be address with this 0x020 register.

You can perform both horizontal and verical scaling operations, with the described adress space, this was already coverd in our vpss example design. You can also refer our video Series29 and XAPP1291 to get a clear picture about the scaling operation. 

Regarding the pixel rate, it should be the gap of the input pixels you need to use to create the output pixel. Also for color modes, we already mentioned the color format and their equalent values in Table3-2, to address the HwReg_ColMode. Please go through it.

I hope it will be helpful to you.

Regards,

Ashok.

Moderator
Moderator
157 Views
Registered: ‎11-09-2015

Re: Register space of Video Processing Subsystem make me confused.

Jump to solution

Hi @wbyjerry 

Aslo pleare refer to the note in the PG231 before the register space:

Note: Control of the video processing pipe is only supported through the Video Processing Subsystem driver. The register map is provided for debug purposes only.

You are expected to use the drivers to control the VPSS. This is the only supported flow.

So you shouldn't have to care about the actual value that have to be programmed in these registers. From a driver point of view, you just have to say what will be your input video format and what will be the output video format and the driver will take care of everything. Please refer to the examples mentioned by @ashokkum 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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