12-06-2018 05:13 AM
I am using SDI TX subsystem ( used the sdi rx subsystem @ zcu106 as ref. design ) on custom made board with US+ 9EG device.
when exporting the HW to SDK I can see the address map correctly assign of both sub cores SDI TX and VTC at xparameters.h , but while executing "configinit "at SDK the VTC is missing , Memory map also show "?????" at Base address + 10000 as assigned for the VTC core .
sdi tx ss base adders is 0xa0000000 , so VTC should be at 0xa0010000 , but it is not .
12-07-2018 11:20 AM
If the address is correct in xparameters.h, then it should also be correct in the code. Can you add some more detail to help us look into this?
12-10-2018 03:00 AM
I am using Vivado 2018.1 with Ubuntu 16.04 OS.
I have attached screenshot with SDK debug running the SDI self test example .
No errors during project build.
SDI SS with all of it's sub cores are visible when viewing implemented schematics.
12-11-2018 07:32 AM
As a double check to see if this is an issue with SDK/xsdb or the code itself, can you print out the values being pushed into the self-test function?
I will try to replicate this on my side on a similar setup.
12-12-2018 03:08 PM
I ran on my side using the passthrough example design from PG290 as hardware. For software, I used the TX self-test function and did not see any issues.
Please verify that your HDF is up to date and that your FPGA is using the correct bitstream.
12-16-2018 12:27 AM
can look into 0x80030000 ?
base address that you are show is working fine on my design . the VTC is not....
The VTC address is mapped with offset of +0x0010000 to the base address of the SDI subsystem core .
12-17-2018 10:17 AM
I do not see any issues on my side with the VTC. My suggestion is that you step through the driver and see where you are getting stuck.
Adding print statements may help as well.
It sounds like your HDF does not match your bitstream.
01-08-2019 01:46 AM
Do you have any updates on this? Did you get all the help you needed from @samk?
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Thanks and Regards,