SDI over GTY

[vykydal]

Hi, gents,

have you anybody experience with SDI video over GTY transceivers? (Kintex ultrascale). Is it possible? What´s the difference compared with GTH? Design for GTH applied to GTY doesn´t work.

Many thanks.

Jiri

[balkris]

you can use XAPP1290

For the UltraScale+ GTH/GTY CPLL, the CPLL calibration block should be used to ensure that the CPLL locks reliably and acquires the correct frequency.

This calibration block is not generated in the GT wizard by default. This will be enabled automatically by the Wizard from Vivado 2017.2 on.

For versions prior to 2017.2, You will need to enable it manually by setting C_INCLUDE_CPLL_CAL to 1:

create_property C_INCLUDE_CPLL_CAL cell -type int

set_property C_INCLUDE_CPLL_CAL 1 [get_cells {*/genblk1[0].sdi_wrapper_support/sdi_wrapper/smpte_3gsdi_gtwiz_i/inst}]
check this ARs as well
https://www.xilinx.com/support/answers/67320.html
Those namings are given for GT primitives.(Gigabit transceivers)
The main difference between GTH and GTY is maximum data rate supported by them.
Please see device data sheet to get the maximum data rates supported by GTH and GTY.

Check below link
http://www.xilinx.com/products/technology/high-speed-serial.html

[florentw]

Hi @vykydal,

As mentioned by @balkris, there shouldn't be much differences between GTH and GTY. So you might use the xapp1290 or the xapp1248 as a reference.

I know that this has been done for some customers on VCU118 (based on the xapp1248) so it is definitely possible.

Regards,

Florent

[vykydal]

Hi, Balkrishan, hi, Florent,

many thanks for you advices, "my" engineers have been working on it; I will give you feedback once we have some results from testbed.

Thank you once again.

Have a nice day.

Jiri

[halakj1]

Hi Florent,

I want to clarify the project details. The project targets SDI signals up to 12G so UHD-SDI IP core is instantiated. We have used XAPP1248 which we were able to use without any problems on KCU105 with GTH transceivers. However our production board will use KU095 chip with GTY transceivers. When we generate GTY IP core for SDI and just use the xapp1248 which is designed for GTH, as we did for KCU105, we are not able to bring it up to work.

From your post, I understand, that the sources from XAPP1248 alone are not enough and they need to be modified to fit for GTYs. Do you have available or plan to make an XAPP for UHD-SDI and GTYs ? If not might you share some recommendations or source codes of the DRP controller which works with GTY?

Thank you,

Regards,

[florentw]

Hi @halakj1,

Do you have available or plan to make an XAPP for UHD-SDI and GTYs ?

> There is currently no plan to do an xapp for UHD-SDI on GTYs (so no official version). The reason for it is because most of our customer are using GTHs. However, you might want to contact your FAE to see if there is something availble but not public (this means that it will come with limited support)

If not might you share some recommendations or source codes of the DRP controller which works with GTY?

> Well, I am not a GT expert. My recommendation is to go through ug476 and ug578 and look for the possible differences between GTX and GTY.

However, my first suggestion here is to contact your FAE.

Regards,

Florent

[florentw]

Hi @vykydal and @halakj1,

Do you have any updates on this?

If everything is clear for you on this subject, please kindly mark it as solved by marking a response as solution.

Kind Regards,

Florent

[kka]

GTY based UHD-SDI example design is released in 2018.1 Vivado for KCU116 platform. 

Refer Chapter 5 of PG290 (https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_rx_ss/v2_0/pg290-v-smpte-uhdsdi-rx-ss.pdf) for more info

[nsilva_mog]

Hi,

I'm reviving this thread as I was trying to implement an SDI design through GTY but on a VCU1525 board. However, I'm getting no results with my implementation.

I tried simulating both my design and all example designs provided by Xilinx, and have noticed that in all cases, the module works (rxoutclk and txoutclk are outputed as well as txn and txp) when the GT IPs are configured to GTH, but don't ever work when configured to GTY.

Furthermore, when simulating the only design configured with GTY, KCU116's loopback example design (I'm only able to simulate since I don't have the board), I found some errors when trying to simulate, a register and a wire were duplicated. This leads me to believe that the example design was not properly tested already to begin with. After fixing the errors, I managed to run the simulation, but the same problem occurs, it works when configured with GTH, but not with the original GTY configuration.

Has anyone managed to implement the provided example design, or can provide some help?

Thanks in advance,

Nuno

[miguelcosta94]

Hi @nsilva_mog,

Have you already find a solution to your problem? I'm facing the same issue when trying to run the example design with the original GTY configuration.

Best regards,

Miguel Costa

[nsilva_mog]

Hi @miguelcosta94,

I did have some advances on reaching a solution.

I managed to get an rxoutclk signal when implementing a GTY transceiver in the VCU1525, but still no txoutclk signal. I tried using the same configuration as the RX configuration, and got no luck. I also tried a bunch of different configs, but no txoutclk signal in sight.

This seems to confirm my theory (and what I saw in simulation), that the GTY transceivers don't seem to be working in regards to their TX component.

I was hoping to get some kind of response on Xilinx's part or if someone had had this problem and managed to solve it, especially since we also sent a ticket to Xilinx support and their response wasn't very helpful. 

Best regards,

Nuno