04-04-2018 04:43 AM
I am working on the implementation of the SMPTE SD/HD/3G-SDI IP on an Atrix-7 AC701 evaluation board.
I want use to generate a HD-SDI format from the RX side and output an SD-SDI format from by the TX side of the IP.
My question that is it possible to generate HD and output an SD format using the same IP? or i have to generate two IPs in vivado, one for the RX HD-SDI and the second for the TX SD-SDI?
Thank you in advance
04-05-2018 08:54 AM - edited 04-05-2018 08:56 AM
Have you had the chance to look at XAPP1097? I believe XAPP1097 is an example on how to implement what you are asking.
XAPP1097 includes 2 demonstrations, a Dual SDI demonstration and a Pass-Through demonstration. The Dual demonstration shows 4 independent interfaces, and I believe you are asking about 2 independent interfaces.
Dual SDI demonstration:
This demonstration application includes two SDI RX interfaces and two SDI TX interfaces that
are all independent. The demonstration is limited to two SDI RX and two SDI TX interfaces
because the AC701 board only connects two GTP transceivers to the FMC connector. This is
not a limitation of the Artix-7 FPGA or the SDI core. It is solely a limitation of this particular
The second SDI demonstration has one SDI RX and one SDI TX connected together in a
pass-through configuration such that the TX always retransmits the data received by the RX
04-06-2018 12:03 AM
Thank you for your return and very valuable explanations.
The question i ask is, for example in case of the Passthrough example, we have an SDI RX and SDI TX, connected together. and suppose the i stream video frames using HD-SDI mode in the RX. Can i transmit these data from the SDI RX to the SDI TX and output it in SD-SDI mode?
The idea is to receive and transmit in different modes for RX and TX using the same SMPTE IP, is it possible or not?
04-06-2018 08:38 AM
The Rx and Tx sides are independent, so you can receive one format and transmit a different format from a different source, or, as a passthrough, you can re-transmit the same Rx source out the Tx side if both sides are set to the same format, for example, 720p60 in to 720p60 out.
However, you are asking if you can receive an HD-SDI (1.485Mb) or 3G-SDI (2.97Mb) signal,on the Rx side and directly connect it to the Tx side and transmit it as SD-SDI (270Mb). The short answer is no, because the two standards don't match, and the SDI core IP does not perform standards conversion. HD-SDI, for instance, would be formatted at 720p60 or 1080i60, and 3G-SDI would be formatted as 1080p60, while the SD-SDI output would have to be formatted as 480i or 576i. The horizontal size of the lines and the vertical size of the frames don't match, and the HD input might be progressive scan while the SD output is interlaced.
If you want to do video standards conversion like this, you would have to receive the HD-SDI signal on the Rx side and use a Video Processing Subsystem IP core to scale the image down to 480p or 576p and then add an interlacer IP to convert it to 480i or 576i, then transmit that image out the SD-SDI Tx core. This requires some DDR3 memory and frame synchronization, which the VPSS core can handle for you. Note that there is no interlacer core IP in Vivado, but it is fairly easy to build one of your own, you can find information on doing that by searching this forum for "interlacer".
One more thing to note: For maximum flexibility, you need to make sure you have two reference clocks, one at 1.485MHz and the other at 1.485/1.001 MHz. This will allow you to receive and transmit all 60Hz/59.94Hz and 30Hz/29.97Hz formats for all five different bit rates.
04-10-2018 07:22 AM
Thank you for this details that give me a good vision about the SMPTE IP capabilities.
My goal is to:
First : Receive 720P HD-SDI video date on the RX side with (74.25/1.001 = 74.18 Mhz)
Second : Make a simple ROI of every frame to have only the video active region, 480 lines and 1280 pixel per line (All blanking is ignored).
Third : Take this active video and apply an interlacing, and in the out put i'll have 480i frames.
Finally : Transmit these interlaced frames on the TX side as SD-SDI (148.5Mhz).
Your explanation is very valuable and clear and resume all, but i have some questions to be sure about the development scheme I'll adopt:
1- After ignoring the blanking while scaling, is it obligatory to develop a sequencer to re-integrate blanking regions? before passing to SD-SDI transmission?
2- Is it possible to not using DDR3 memory? I mean, Data processing by scaling block, directly passed to interlacing block without memorization, after interlacing data go through asynch FIFO to pass from HD clock domain to SD clock domain then sned it to SD-SDI TX?
Thank you in advance for your return.
04-13-2018 12:53 AM
1. You need to reformat the data properly for the TX IP
2. Yes you should be able to do this without external memory. But it will depend on the device you chose. You might be tight in ressources.
04-17-2018 01:16 AM
Is everything clear for you on this subject? If yes, please kindly close the topic by marking one reply as accepted solution.
Thanks and Regards,