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Observer tmiller
Observer
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Registered: ‎10-24-2017

SMPTE UHD-SDI Pixel Mapping

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Hello,

I'm interested in using the SMPTE UHD-SDI Transmitter Subsystem v2.0 (https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_tx_ss/v2_0/pg289-v-smpte-uhdsdi-tx-ss.pdf) in order to send a custom stream of data via SDI. However, one thing that is not mentioned in the document is the mapping of the input pixels on to the 80-bit virtual interface described on page 7 of the document.

If the video input to the core is YUV422, the core receives Y0, U0, Y1, V0, Y2, U1, Y3, V1 on the native video interface. Do these map directly on to the 80-bit interface as Y0 -> Channel 0, U0 -> Channel 1 etc?

SMPTE ST2082-10:2018 does describe a mapping (section 4.1.2) of YUV422 onto the data channels. However, this maps the pixel values from two adjacent rows simultaneously onto the 8 data channels. If this is what the core is doing, it is presumably internally buffering a whole row of data?

Please advise.

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Moderator
Moderator
540 Views
Registered: ‎10-04-2017

Re: SMPTE UHD-SDI Pixel Mapping

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Hi @tmiller,

 

The bus width of 64 is a maximum, so a conclusion on the PPC (pixels per clock) or bits per pixel cannot be made based on the width alone.

The core outputs YUV422 or 420, 10Bit, and it is also 2PPC as set by the video bridge.

 

Please use UG934 as a guide on YUV422.

 

Regards,

Sam

 

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Moderator
Moderator
743 Views
Registered: ‎10-04-2017

Re: SMPTE UHD-SDI Pixel Mapping

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Hi @tmiller,

There are two ways to interface to the core. AXI and NATIVE.

For AXI, these follow the AXI protocol. 

2019-01-23 15_27_49-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

For NATIVE, these follow the SMPTE standard. See chrisar's replies in this post.

2019-01-23 15_30_21-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

 

Regards,

Sam

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Observer tmiller
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Registered: ‎10-24-2017

Re: SMPTE UHD-SDI Pixel Mapping

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Hi @samk

What I don't understand is what order pixel data should be placed on the AXIS bus in order to create, for example a ST2082-10 mode 1 4:2:2 mapping. There are 64 bits on the input, but how the input data should be structured within these 64 bits, or even how many pixels are input each clock cycle, is not clear to me from the documentation.

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Moderator
Moderator
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Registered: ‎10-04-2017

Re: SMPTE UHD-SDI Pixel Mapping

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Hi @tmiller,

 

If you are using the AXIS interface and not the Native interface, the interfacing only needs to follow AXIS protocol for Video and not the ST standards. 

 

This takes your question an makes it: How do I do I transfer 4:2:2 over AXIS? To answer this, please see Reference 10, UG934.

UG934 has diagrams and explanations on how to structure 4:2:2 based on pixels per clock and bits per component.

 

Here is an example for 2 pixels per clock and 12 bits.

image.png

Regards,

Sam

 

 

 

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: SMPTE UHD-SDI Pixel Mapping

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Hi @tmiller,

Do you have any updates on this? Were @samk's replies enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer tmiller
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Registered: ‎10-24-2017

Re: SMPTE UHD-SDI Pixel Mapping

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I still don't think I understand.

I'm aware of UG934, however I'm not sure this is sufficient to answer my question, because there is no information on how many pixels per cycle, or how many bits / pixel the internal AXI4-Stream to Video-Out IP will be configured for when the AXI4-Stream input is selected. The interface is 64 bits wide. I would have probably expected that two 10 bit YUV422 pixels/cycle would result in a 40 bit interface, so this doesn't offer any clues.

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Moderator
Moderator
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Registered: ‎10-04-2017

Re: SMPTE UHD-SDI Pixel Mapping

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Hi @tmiller,

 

The bus width of 64 is a maximum, so a conclusion on the PPC (pixels per clock) or bits per pixel cannot be made based on the width alone.

The core outputs YUV422 or 420, 10Bit, and it is also 2PPC as set by the video bridge.

 

Please use UG934 as a guide on YUV422.

 

Regards,

Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub