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Contributor
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Registered: ‎10-01-2013

Sensor Demosaic core fails synthesis

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Using Vivado 2017.4, I configured the Sensor Demosaic core for 8 pixels/clock, 12 bit pixels, 3216x2208 resolution.  Out of context synthesis sometimes fails with the error below.  Strangely, it does not fail every time.  Sometimes I can reconfigure the settings and it works.

 

INFO: [HLS 200-10] Checking synthesizability ...

ERROR: [SYNCHK 200-41] c:/<snip>/sources_1/ip/v_demosaic_0/src/v_demosaic.cpp:248: unsupported pointer reinterpretation from type '[5 x i36]*' to type 'ap_axiu<288, 1, 1, 1>' on variable '.023348'. 
WARNING: [SYNCHK 200-23] c:/<snip>/sources_1/ip/v_demosaic_0/src/v_demosaic.cpp:256: variable-indexed range selection may cause suboptimal QoR. 
INFO: [SYNCHK 200-10] 1 error(s), 1 warning(s). 
ERROR: [HLS 200-70] Synthesizability check failed.

 

XCI config file attached.  It synthesizes successfully if I select 8 bit pixels. 

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Moderator
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Registered: ‎11-09-2015

Re: Sensor Demosaic core fails synthesis

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Hi @bkuschak,

 

I was only able to reproduce the issue on Windows OS. Could you confirm this is the OS you are using?

 

If yes, could you try the patch from AR#70445 or move to 2018.1 (fix integrated). It seems to fix the issue.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: Sensor Demosaic core fails synthesis

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Hi @bkuschak,

 

What OS are you using?

Could you try to find a vivado_hls.log under the IP OOC synthesis folder (under synth_1\IPname) whem it fails and attach it to this topic?

Could you also provide the vivado.log file (enter pwd in the tcl console to know where it is created)?

And the .xci file of the IP.

 

EDIT: I was able to repproduce the issue on WIN7. I am investigating.

 

Regards,

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: Sensor Demosaic core fails synthesis

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Hi @bkuschak,

 

I was only able to reproduce the issue on Windows OS. Could you confirm this is the OS you are using?

 

If yes, could you try the patch from AR#70445 or move to 2018.1 (fix integrated). It seems to fix the issue.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎10-01-2013

Re: Sensor Demosaic core fails synthesis

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Hi Florent, thanks for the reply.

I am running Windows 10.  I'm not sure if it matters, but I'm not using HLS.  I am instantiating the core in Verilog. 

I will try the patch, but as I said, it seemed to complete synthesis successfully the last time I ran it.  I'm not sure why the failure is intermittent.

 

 

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Registered: ‎11-09-2015

Re: Sensor Demosaic core fails synthesis

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Hi @bkuschak,

 

I am running Windows 10.  I'm not sure if it matters, but I'm not using HLS. 

> The demosaic core is what we called an hls based IP. It is written in c (or c++) and when you had it to vivado, it calls hls in the background. No matter how you instantiate the IP.

 

I will try the patch, but as I said, it seemed to complete synthesis successfully the last time I ran it.  I'm not sure why the failure is intermittent.

> I will try multiple run with the patch and see if I can make it fail. Please let me know the results on your side

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: Sensor Demosaic core fails synthesis

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Hi @bkuschak,

 

With the configuration 8 pixels/clock, 12 bit pixels, 3216x2208 resolution:

  • With the patch: I tried to genererate the Output Products 10 times amd I have no failure
  • Witout the patch : I tried only 3 times but it is failing each time

So it seems to confirm that the patch is fixing the issue.

 

I will try the patch, but as I said, it seemed to complete synthesis successfully the last time I ran it.  I'm not sure why the failure is intermittent.

> From what I have seen from previous issues fixed by the patch, the issues are only happening in some particular configuration. So it might have work with 1 pixels/clock or other ppc settings.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: Sensor Demosaic core fails synthesis

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Hi @bkuschak,

 

Any updates from you? Did you try the patch?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎10-01-2013

Re: Sensor Demosaic core fails synthesis

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Perhaps not surprisingly it did not go smoothly. I applied the patch as directed, and tried to regenerate the core. The out of context synthesis failed.  There was this message (paths shortened):

 

reset_target all [get_files C:/<snip>/sources_1/ip/v_demosaic_0/v_demosaic_0.xci]
export_ip_user_files -of_objects [get_files C:/<snip>/sources_1/ip/v_demosaic_0/v_demosaic_0.xci] -sync -no_script -force -quiet
delete_ip_run [get_files -of_objects [get_fileset v_demosaic_0] C:/<snip>/sources_1/ip/v_demosaic_0/v_demosaic_0.xci]
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory C:/<snip>.runs/v_demosaic_0_synth_1

 

I removed the core from the project, manually deleted the ip/v_demosiac_0 directory and re-added the core again. Clicked Generate to start the out of context synthesis. Nothing happens, and the core is not listed in the Design Runs window.  I see this message in the console:

 

INFO: [Vivado 12-3453] The given sub-design is up-to-date, no action was taken. If a run is still desired, use the '-force' option for the file:'C:/<snip>.srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci'

 

I ran it manually with the -force option and it now shows up in the Designs Runs list as "Not Started".

 

create_ip_run -force [get_files -of_objects [get_fileset sources_1] C:/<snip>.srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci]
v_demosaic_0_synth_1

 

So I right click 'Generate output products' and I get the same INFO message:

 

reset_target all [get_files C:/<snip>srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci]
export_ip_user_files -of_objects [get_files C:/<snip>srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci] -sync -no_script -force -quiet
delete_ip_run [get_files -of_objects [get_fileset v_demosaic_0] C:/<snip>srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci]
INFO: [Project 1-386] Moving file 'C:/<snip>srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci' from fileset 'v_demosaic_0' to fileset 'sources_1'.
generate_target all [get_files C:/<snip>srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'v_demosaic_0'...
INFO: [IP_Flow 19-1686] Generating 'High-Level Synthesis C source' target for IP 'v_demosaic_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'v_demosaic_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'v_demosaic_0'...
WARNING: [IP_Flow 19-1971] File named "sim/v_demosaic_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'v_demosaic_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'v_demosaic_0'...
catch { config_ip_cache -export [get_ips -all v_demosaic_0] }
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP v_demosaic_0, cache-ID = 0fdcbfe78d0ca379; cache size = 326.907 MB.
config_ip_cache: Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1285.836 ; gain = 102.035
export_ip_user_files -of_objects [get_files C:/<snip>srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] C:/<snip>srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci]
INFO: [Vivado 12-3453] The given sub-design is up-to-date, no action was taken. If a run is still desired, use the '-force' option for the file:'C:/<snip>srcs/sources_1/ip/v_demosaic_0/v_demosaic_0.xci'

 

Looking in the directory, files have been generated, including a .dcp file. But it was extremely quick, about 10 seconds. Not the several minutes I would have expected a real build to take. And once again it has disappeared from the Design Runs list. It looks like it might be using old cached results of the previous synthesis.

 

In reference to my earlier comment about it having built seemingly successfully once prior to applying the patch, see the first screenshot.  This was built with the same settings that caused it to fail the first time. Of course, now having applied the patch, I can't seem to get back to that state..

 

So I tried to clear the cache, and then reset and regenerate the core.  

 

config_ip_cache -remove [get_ips -all v_demosaic_0]

 

That seems to do the trick.  The core built successfully, and the resulting utilization is a bit bigger than it was the first time.  See the second screenshot.  

 

Thanks for your help!

 

demosaic_before_regen.PNG
demosaic_after_patch_and_regen.PNG
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Registered: ‎11-09-2015

Re: Sensor Demosaic core fails synthesis

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Hi @bkuschak,

 

Thank you for letting me know.

 

Yes when doind the tests, I have manually removed the .cache, .ip and .runs folder to prevent vivado from using previous files.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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