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Participant canonind
Participant
1,756 Views
Registered: ‎05-08-2013

Simple MIPI CSI-2 TX System

Hi,

 

Using Vivado 2018.1 in Windows 10 64-bit, I am trying to implement a simple MIPI TX system using the Xilinx MIPI CSI-2 Tx Subsystem (2.0). I have setup a simple system shown here:

 

BD.PNG

I am using the TPG IP to generate a horizontal ramp video stream. I have configured the MIPI IP like this:

 

MIPI_TX_IP_1.PNG

 

MIPI_TX_IP_2.PNG

 

I have also written a simple AXI4-Lite Controller to be able to access the registers of the IPs for the simulation. This works fine and I am able to verify the values of the MIPI and TPG IP core registers (Default values as well as the values I have written are fine).

 

In the testbench:

 

1) Set the rows & cols for TPG to 3 (Reg x10 -> 00000003, Reg 0x18 -> 0x00000003)

2) Set the background pattern to horizontal ramp for TPG (Reg 0x20 -> 0x00000001)

3) Enable the MIPI core and assert soft reset (Reg 0x00 -> 0x00000003)

4) Deassert soft reset for the MIPI core (Reg 0x00 -> 0x00000001)

5) Kick off the TPG core to send some stream data (Reg 0x00 -> 0x00000001)

 

From the waveform I can see that the MIPI signals the Tready to TPG so that it can start sending data. The TPG also sends its 3 rows, so the communication between MIPI and TPG is there:

 

Waveform.png

 

However 2 problems:

1) At the output of the MIPI, I see constant '1' s, although the incoming stream from the TPG is correct.

2) When I read back the MIPIs Core configuration register (0x00), I see that Bit 2 is 0, which means the core is not ready. That is also probably why I am seeing those 1s.

 

Any ideas why this can be happening? Also worth mentioning is that during the GUI configuration of the MIPI core I have choosen the shared logic option, because otherwise I had to supply all the clocks myself. In this way I just provide the 200 MHz and the core takes care of the rest. Am I misinterpreting this? Do I have to do some additional things?

 

Thanks,
Berk

 

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11 Replies
Participant canonind
Participant
1,702 Views
Registered: ‎05-08-2013

Re: Simple MIPI CSI-2 TX System

I read the DPHY documation (PG202 v3.1) again and saw that there is a DPHY-TX Init Timer Register. Default value is set to 1000 ms. I thought that is maybe the reason why the core gets not ready by the time I read the register 0x00 Bit 2. So I set this timer register to 1000 nanoseconds. But still I am getting 0 on Bit 2.

 

Any other ideas?

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Simple MIPI CSI-2 TX System

Hi @canonind,

 

You might want to make sure you are carefully following the section MIPI CSI-2 TX Controller Core Programming of the MIPI CSI-2 TX Product Guide (PG260)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
1,665 Views
Registered: ‎03-30-2016

Re: Simple MIPI CSI-2 TX System

Hello @canonind

 

I believe you will not be able to send data, by simply connecting TPG s_axis_*** to MIPI TX IP s_axis_**** .

 

1. Please check PG260 appendix B, figure B-2, on how to send HS data using MIPI TX-2 IP.

2. Please share your MIPI CSI-2 TX IP stream input interface s_axis_***** ?

    -- user has to assert tuser[0]=1 to trigger SoT (Start of frame). before sending the first HS packet.

       many new MIPI user did not realize this requirement.

3. I see from your sim result that you s_axis_tready is still "0". It means MIPI CSI-2 TX IP is not ready to accept any data.

    Please wait until s_axis_tready=high before sending data from TPG.

 

Best regards
Leo

Participant canonind
Participant
1,640 Views
Registered: ‎05-08-2013

Re: Simple MIPI CSI-2 TX System

Hello Florent,

Hello Leo,

 

Thank you for your answers.

 

 1) The problem was that I was waiting not long enough. I had to wait 1 ms even in simulation for the core to be ready. But is there no way to decrease this time for the simulation?

 

2) You are right about TPG and MIPI I guess. Right now the interface between them looks like this:

 

interface_tpg_mipi.png

 

For example, the TUSER width does not match at all, which means that all the information required by the MIPI is not supplied!

 

But at this point, can you suggest any other core than TPG to send data to MIPI or would you suggest writing a VHDL module to match the MIPI side?

 

Best Regards,

Berk

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Xilinx Employee
Xilinx Employee
1,543 Views
Registered: ‎03-30-2016

Re: Simple MIPI CSI-2 TX System

Hello @canonind

 

Thank you very much for your update.

 

1. But is there no way to decrease this time for the simulation?

    Currently, no (unfortunately).
    You can try to use 3rd party simulator other than Vivado, if you have the license.
    We have same request from other customer regarding simulation time, our development team are considering for some improvement.

 

2. I think AXI Traffic Generator (ATG) will be a better option. Please check PG125 for more detailed info.

    but If you can design a custom Pattern generator, it will be good.

 

Thanks & regards

Leo

Moderator
Moderator
1,496 Views
Registered: ‎11-09-2015

Re: Simple MIPI CSI-2 TX System

Hello @canonind,

 

This topic is still open and is waiting for you.

If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant canonind
Participant
1,392 Views
Registered: ‎05-08-2013

Re: Simple MIPI CSI-2 TX System

Hi,

 

Sorry I was busy following Leo's suggestion and implementing the custom AXI Stream generator that is compatible with the MIPI TX IP input. It took a little bit time :)

 

Now that a dummy gen + TX system is working, I also added a MIPI RX core to have a simulation loopback. So I generate the data, send it through the TX and I am also able to see the data at the output of the RX core after asserting it's TREADY. It is all fine. However one question here: Although the data is correct, the sideband info (TUSER, containing the frame start, line number, ...) is constantly 0 as depicted below:

 

TUSER.png

 

Also the line number and frame number sections of the TUSER are constantly 0. However from Word Count section I can see the correct value so it is not like TUSER is completely dead.

 

Another issue is that I started to implement the design (changed the bd a bit. Now I don't have the loopback TX to RX. TX sends out the data, RX receives these data as input from outside. The idea is to test the system on the ZCU102 with a Whizz FMC Loopback card). However when I implement the design, it gives the following error:

 

[Place 30-687] Expected cell top_mipi_system_inst/MIPI_CSI2_Sim_System_i/mipi_csi2_rx_subsyst_0/U0/phy/inst/bd_fb84_phy_0_rx_support_i/slave_rx.bd_fb84_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[39].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.

 

I made the pin assignments through the GUI:

 

Pin_Assignment.png

 

I thought the core generates all the constraints needed through these settings. But are there any other settings need to be written in the .xdc file manually?

 

Thanks & Regards,

Berk

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Xilinx Employee
Xilinx Employee
1,374 Views
Registered: ‎03-30-2016

Re: Simple MIPI CSI-2 TX System

Hello Berk @canonind


Your simulation result does not look good.
- tlast which indicate last data of the line, asserted many times in a singe lanes
  I believe your TX  has a problem with buffer underrun/overflow.
- Please see that rxactivehs is toggling when sending 1 line of video data.
  MIPI should stay at HS mode when sending 1 packet of data.
- Please check your TX clock setting is good. You may also to re-check PG260 Chapter3, Clocking section.
  It has some guideline on the s_axis_aclk frequency depending on your use-case.
- Please ensure your Interupt Status register of MIPI TX is good.
We can discuss about your TUSER behavior after we can solve the problem above.

 

- About the Implementation error:
  MIPI CSI-RX Wizard should be generated all requeires constraint for MIPI IP.
  Could you please check if you have missed any XDC file or has over-write MIPI IP pin-assignment constraint ?
  If it does not solve the problem, maybe we can involve Vivado expert to help.

 

Thanks & regards
Leo

Participant canonind
Participant
1,330 Views
Registered: ‎05-08-2013

Re: Simple MIPI CSI-2 TX System

Hello Leo,

 

About simulation:

Sorry for the confusion, the waveform is a bit misleading. Line0 consists of 3 different part where end of each part a TLAST should be sent. I made this in my training pattern generator like this and this is how I want TLAST to behave actually.

 

Line 0:

part1 -> 32 bytes @ the end 1 cycle TLAST

part2 -> 64 bytes @ the end 1 cycle TLAST

part3 -> 708 bytes @ the end 1 cycle TLAST

 

About Implementation:

 

 

I double checked and verified, I do not have any other xdc files apart from the ones that are generated by the core. One thing I noted was that I also get these warnings:

 

MIPI_Pin_LOC_Warnings.PNG

 

These warnings also refer to the core generated xdc files and one line in the xdc is for example like this.

 

set_property PACKAGE_PIN AJ12 [get_ports clk_txp]

 

I tried the get_ports clk_txp command on the TCL console in the elaborated design, but I can find the clk_txp. So it's not like the tool optimizes it out.

 

Can this be a VIVADO 2018.1 issue maybe?

 

Thanks & Regards,

Berk

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Xilinx Employee
Xilinx Employee
738 Views
Registered: ‎03-30-2016

Re: Simple MIPI CSI-2 TX System

Hello Berk @canonind

 

>Sorry for the confusion, the waveform is a bit misleading. Line0 consists of 3 different part where end of each part a TLAST should be sent. I made this in my training pattern generator like this and this is how I want TLAST to behave actually.

 

1. Okay, if you set MIPI TX to behave like above, then no problem the IP works as expected.

2. Frame number is sent by Frame Start synchronization short packet.

    Could you please check whether MIPI TX send those packet when you assert tuser[0] on the TX side ?

    I can check if you can share the sim result.

3. I do not aware of any issue on 2018.1 MIPI IP. regarding the Critical warning you have sent us.

    It is possible to share the DCP file ?

  

Thanks & regards

Leo

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Moderator
Moderator
644 Views
Registered: ‎11-09-2015

Re: Simple MIPI CSI-2 TX System

Hi @canonind,

 

Do you have any updates? Any solution you can share with the community?

 

Thanks and regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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