UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor addi
Visitor
1,286 Views
Registered: ‎11-15-2018

Spartan 6 IP core Video image processing

Jump to solution

Dear Friends!

Can anybody say which video image processing IP core will be usefull in conversion of ADC data of luma(Y I suppose) from pixels of infrared matrix array(FPA)?

It is necessary cause Im going to transfer "infrared video" to VLC player 

0 Kudos
1 Solution

Accepted Solutions
Scholar watari
Scholar
817 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

Sorry. It was not enough information for you.

So, I mention them again.

 

1. timing diagram

 

You should design detector logic with Vout_EN.

I guess you design RTL code with state machine which detect or/and generate sync signals.

 

2. color space

I guess you want to get RGB data. However you only receive Y.

So you need to change color space with ex. ITU BT. 709 color space (parameter).

 

Best regards,

 

 

0 Kudos
21 Replies
Moderator
Moderator
1,249 Views
Registered: ‎11-09-2015

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi,

This paper seems to describe what you are looking for:

https://www.researchgate.net/publication/233864765_Processing_of_the_image_from_infrared_focal_plane_array_using_FPGA-based_system


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Visitor addi
Visitor
1,223 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Dear florentw!

Thank you for your link but my question is still staying
Because Ive got FPA with just analog output without contol or sync signals.
Analog video digitized by A/D converter and FPGA gets digital value of pixels (Luma) - 640x480 = 307200 14-bits values of pixels.
I need to transfer these data through W5300 to PC VCL Player.
But before do it I have to do conversion under 307200 14-bits values of pixels to be recognized by UDP LAN Video for VLC player.
I though that I can do from 307200 14-bits values of pixels video format using Xilinx IP cores.
Now I still searching the decision..

0 Kudos
Scholar watari
Scholar
1,218 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

> Because Ive got FPA with just analog output without contol or sync signals.

 

It's strange. At least, the design requests sync signal or frame start signal.

If it doesn't have any control and sync signals, how do you synchronize Y data ?

 

Best regards,

 

0 Kudos
Visitor addi
Visitor
1,211 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Dear Watari!

Yes you are right, Ive got frame sync signal, I meant that I havent got hsync and vsync signal, only Vout_EN and VOUT

0 Kudos
Scholar watari
Scholar
1,183 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

You can generate vsync, hsync, data enable signals with signal detector from Vout_EN and VOUT.

 

Best regards,

 

0 Kudos
Visitor addi
Visitor
1,170 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Dear Watari!

Mayby  you have known does Xilinx have appropriate IP core to do this conversion?

0 Kudos
Scholar watari
Scholar
1,155 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

I don't know whether Xilinx already released like this IP or not.

However, it is easy to generate these signals by yourself.

ex. "hsync" signal is generated by inverted Vout_EN.

 

Best regards,

0 Kudos
Visitor addi
Visitor
1,140 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Dear Watari!

Thank you, now I starting understanding, but left one monent - how to generate from digitized analog voltage from FPA - Y', Cr, Cb ?

0 Kudos
Scholar watari
Scholar
1,133 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

> how to generate from digitized analog voltage from FPA - Y', Cr, Cb ?

 

Sorry. I can not understand what you want to do and explain detail.

Because of it doesn't satisfy to reply it to you.

 

Would you share me your environment  and explain it,  too ?

 

Best regards,

0 Kudos
Moderator
Moderator
1,129 Views
Registered: ‎11-09-2015

Re: Spartan 6 IP core Video image processing

Jump to solution

HI @addi,

What is the interface you are using to receive Y Cb Cr? Is it through SDI?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Visitor addi
Visitor
1,121 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Thanks Friends!

Sorry maybe I wrong in explanation, I have got infrared Focal plane array, 14 A/D converter, and Spartan 6 and wiznet W5300

FPA gets on output just analog voltage

I though I can do digitalization, convertation to the video standart and futher transfer to VLC player as LAN stream by UDP

Please correct me

0 Kudos
Scholar watari
Scholar
1,094 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

As you mentioned before, the important points are Vpp spec. on ADC and the degitalized range of video data.

If you already considered them, I suggest the following flow.

 

1. Receive degitalized data from ADC with suitable IO buffer.

2. Implement matrix logic in FPGA and set the parameter. ex. ITU BT. 709 colorimetric. (color space) (from Y to RGB color space)

3. Some application, like VLC, encode video data and output it via Ethernet.

 

Best regards,

 

0 Kudos
Visitor addi
Visitor
1,076 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Dear Watari !

Thank you for your support

Yes I have done it 5V, 40 Mhz

About your steps, I will do this , but left one question - how to convert analog voltage of analog video signal to YCrCb?

I found Xilinx IP YCrCb to RGB color space converter which helps futher

0 Kudos
Scholar watari
Scholar
1,065 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

As you already mentioned before, you can only get luma as Y.

So, Cr and Cb are zero.

 

Best regards,

 

0 Kudos
Visitor addi
Visitor
1,063 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Dear Watari!

Thanks a lot, understand

Maybe you have known which timing diagram I should to use within conversion analog voltage of pixels to YCrCb?

Thanks in advance

0 Kudos
Scholar watari
Scholar
1,056 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

> Maybe you have known which timing diagram I should to use within conversion analog voltage of pixels to YCrCb?

Yes. 

 

BTW, if you understand or find the solution, could you close this issue ?

Also, if you have another question, would you post new thread ?

 

Best regards,

 

0 Kudos
Visitor addi
Visitor
1,042 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Dear Watari!

Rest one quedtion telated to topic about timing disgram, and also I dont known how to close issue in futher

0 Kudos
Highlighted
Scholar watari
Scholar
916 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

What kind of signals do you receive ?

Only Vout_EN and Vdata ?

 

If yes, as I already mentioned before, you should implement detector logic.

 

Best regards,

0 Kudos
Visitor addi
Visitor
899 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Dear Watari!

 

Thank you for your support

Yes.

Under detector logic you meant - "Implement matrix logic in FPGA and set the parameter. ex. ITU BT. 709 colorimetric. (color space) (from Y to RGB color space)"?

0 Kudos
Scholar watari
Scholar
818 Views
Registered: ‎06-16-2013

Re: Spartan 6 IP core Video image processing

Jump to solution

Hi @addi

 

Sorry. It was not enough information for you.

So, I mention them again.

 

1. timing diagram

 

You should design detector logic with Vout_EN.

I guess you design RTL code with state machine which detect or/and generate sync signals.

 

2. color space

I guess you want to get RGB data. However you only receive Y.

So you need to change color space with ex. ITU BT. 709 color space (parameter).

 

Best regards,

 

 

0 Kudos
Visitor addi
Visitor
807 Views
Registered: ‎11-15-2018

Re: Spartan 6 IP core Video image processing

Jump to solution

Thanks a lot!!

0 Kudos