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Visitor tomaho
Visitor
4,865 Views
Registered: ‎02-23-2010

Standard rules for video processing FPGA architecture ?!?!

Hello,

 

i´m trying to find an FPGA architecture for video processing.

Though my experience is still quite little i´d be glad of some advice.

One of the architecture requirements is flexibilty: When putting it into practice i need my architecture to get expanded very easily e.g. by further IP Cores.

As a consequence i think i should use a bus system in any case and probably an intelligence like MicroBlaze, too or are there better options?

 

Originally my plan was to input two video streams (1024x768 pixels each, at 60Hz) process them with Xilinx OSD and filter again the result of that.

So to filter a stream of that size i always need to buffer some lines at first, but isn´t the resolution much to high to do that?

Buffering three lines in RGB are 3 x 1024 x 768 x 24 bit > 73kBit which is more than even a Virtex-6 offers BRAM (max 39kBit ).

Is it common using BRAMS for that purpose or shall better external memory take this task over?

But when using external memory the bus system is again required and especially the MPMC which brings my original video data in.

 

Generally I just don´t know yet how to put different graphics processing IP Cores together with all the memory ´stuff´ like DDR, BRAM/FIFO and MPMC, VDMA and bus system in architecture.

 

 

Regards,

tomaho

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2 Replies
Visitor newenging
Visitor
4,169 Views
Registered: ‎02-07-2011

Re: Standard rules for video processing FPGA architecture ?!?!

Have you considered using Xilinx Spartan Industrial Video Processing kit's technical docs as reference?

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Teacher eteam00
Teacher
4,167 Views
Registered: ‎07-21-2009

Re: Standard rules for video processing FPGA architecture ?!?!

@newenging

Have you considered using Xilinx Spartan Industrial Video Processing kit's technical docs as reference?

Have you considered you woke up a thread which was almost a year old?  :)

 

- Bob Elkind

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