UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
442 Views
Registered: ‎09-25-2017

Swap polarity MIPI D-Phy HS LVDS input

Jump to solution

Setup:

  Vivado 2018.3

  Kintex-7

  MIPI CSI-2 Rx Subsystem 4.0

  Is there a way to swap P and N HS LVDS inputs in the IP configuration so that externally sensor datalane_p can be connected to FPGA LVDS_N as such.

  Is there a similar option for HS MIPI CLK input too?

 

Regards,

Neo

 

 

Tags (2)
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
396 Views
Registered: ‎03-30-2016

Re: Swap polarity MIPI D-Phy HS LVDS input

Jump to solution

Hello Neo wtneo@leica 

1. Unfortunately, XILINX MIPI D-PHY IP does not support P/N swap. ( at least for current release 2019.1, 2019.2)
    -- C_DL**_IO_SWAP is a hidden parameter for internal debug. Please ignore.
2. Sorry I cannot help on this and I do not suggest this, but manual netlist modification could be possible.
    ( For example swapping O/OB port connectivity of IBUFDS_DIFF_OUT )
   

Thanks & regards
Leo

View solution in original post

3 Replies
Explorer
Explorer
425 Views
Registered: ‎09-25-2017

Re: Swap polarity MIPI D-Phy HS LVDS input

Jump to solution

I found a few properties for MIPI D-Phy in block diagram that seem to support inverting LVDS P and N input.  They are:

  1. C_DL0_IO_SWAP
  2. C_DL1_IO_SWAP
  3. C_DL2_IO_SWAP
  4. C_DL3_IO_SWAP
  5. C_CLK_IO_SWAP

Setting these properties to true, I am able to assign IP core's data input N port to P pin of FPGA's LVDS pairs.

I studied post bitgen schematics and found that Vivado physically swapped the N and P  signals before input to IBUFS.  See attached screen capture.  For example in attached schematic I set C_DL1_IO_SWAP = true.  The rest of the lanes are not swapped.

However, does MIPI D-Phy IP internally logically "NOT" the data from this lane such that it is the same polarity as other lanes?  Or MIPI D-Phy automatically detects the lane inversion during link training and handles that, much like AUTO-MDIX in Ethernet.

Regards,

Neo

schematic of C_DL1_IO_SWAP true.PNG
0 Kudos
Xilinx Employee
Xilinx Employee
397 Views
Registered: ‎03-30-2016

Re: Swap polarity MIPI D-Phy HS LVDS input

Jump to solution

Hello Neo wtneo@leica 

1. Unfortunately, XILINX MIPI D-PHY IP does not support P/N swap. ( at least for current release 2019.1, 2019.2)
    -- C_DL**_IO_SWAP is a hidden parameter for internal debug. Please ignore.
2. Sorry I cannot help on this and I do not suggest this, but manual netlist modification could be possible.
    ( For example swapping O/OB port connectivity of IBUFDS_DIFF_OUT )
   

Thanks & regards
Leo

View solution in original post

Contributor
Contributor
101 Views
Registered: ‎03-11-2016

Re: Swap polarity MIPI D-Phy HS LVDS input

Jump to solution

Adding to this knowledge, the way I work around the problem is applying the following constraints to the OSERDES in DPhy.

# flip PN for lane 2
set_property IS_D1_INVERTED 1'b1 [get_cells -hierarchical dl2_obufds_inst.dl2_oserdese2_master] set_property IS_D2_INVERTED 1'b1 [get_cells -hierarchical dl2_obufds_inst.dl2_oserdese2_master] set_property IS_D3_INVERTED 1'b1 [get_cells -hierarchical dl2_obufds_inst.dl2_oserdese2_master] set_property IS_D4_INVERTED 1'b1 [get_cells -hierarchical dl2_obufds_inst.dl2_oserdese2_master] set_property IS_D5_INVERTED 1'b1 [get_cells -hierarchical dl2_obufds_inst.dl2_oserdese2_master] set_property IS_D6_INVERTED 1'b1 [get_cells -hierarchical dl2_obufds_inst.dl2_oserdese2_master] set_property IS_D7_INVERTED 1'b1 [get_cells -hierarchical dl2_obufds_inst.dl2_oserdese2_master] set_property IS_D8_INVERTED 1'b1 [get_cells -hierarchical dl2_obufds_inst.dl2_oserdese2_master]
# flip PN for lane 3 set_property IS_D1_INVERTED 1'b1 [get_cells -hierarchical dl3_obufds_inst.dl3_oserdese2_master] set_property IS_D2_INVERTED 1'b1 [get_cells -hierarchical dl3_obufds_inst.dl3_oserdese2_master] set_property IS_D3_INVERTED 1'b1 [get_cells -hierarchical dl3_obufds_inst.dl3_oserdese2_master] set_property IS_D4_INVERTED 1'b1 [get_cells -hierarchical dl3_obufds_inst.dl3_oserdese2_master] set_property IS_D5_INVERTED 1'b1 [get_cells -hierarchical dl3_obufds_inst.dl3_oserdese2_master] set_property IS_D6_INVERTED 1'b1 [get_cells -hierarchical dl3_obufds_inst.dl3_oserdese2_master] set_property IS_D7_INVERTED 1'b1 [get_cells -hierarchical dl3_obufds_inst.dl3_oserdese2_master] set_property IS_D8_INVERTED 1'b1 [get_cells -hierarchical dl3_obufds_inst.dl3_oserdese2_master]

I have verified on hardware with Zynq 7 C1 device overclocked beyond 1.4Gbps. Receiver end is RK3399.