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Visitor emotal
Visitor
1,525 Views
Registered: ‎06-19-2017

Synchronizing video signals with AXI4-Stream to Video

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Does 'AXI4-Stream to Video' IP always miss first three video frame to get fully synchronized with video output signals?
When I look at the video signal outputs of 'AXI4-Stream to Video' IP through ILA, 'locked' signal got high on the third video frame.
'locked' signal does not get high during first two video frames.

At third frame, 'locked' signal is high, but output video signals are not synchronized yest.

with starting fourth frame, all video signals are synchronized.
Is this normal? or is not supposed to be?
I use 'AXI4-Stream to Video' IP as a master mode, and video data stored in DDR3 memory.

A VDMA is sitting between DDR memory controller (via HPs port) and 'AXI4-Stream to Video' IP in Zynq7020.

 

Thanks

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Xilinx Employee
Xilinx Employee
1,468 Views
Registered: ‎08-02-2007

Re: Synchronizing video signals with AXI4-Stream to Video

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@emotal

If the VtC timing matches the frame size from AXI4 Stream Video interface, it should be locked within a whole frame. if the SOF from VTC is too fast, it detects two sof from VTC, but no tuser from AXI4 Stream interface, it won't lock until you fix the frame size errors.

 

When you use it in master mode, it means VTC is timing master, in this case, it expects video stream coming from AXI4 Stream interface is free running, you can capture the Video Timing, Video AXI4 Stream interface in ILA, and check which is too fast, probably you need to slow down.

 

So the thing to check : 

1. HSize, Vsize register of VDMA read side, and see if it matches the settings in VTC

2. read side of VDMA is free run mode

 

As your Video stream is from VDMA, it could have SOF/EOL errors at read side at the beginning, you can double check this in the VDMA Status register at read side. If you do see error bits asserted, I think the problem is more at VDMA side rather than AXI4-Stream to Video Out side.

 

You can start with the test that contains VTG, VTC, AXI4-Stream to Video Out, if it doesn't have such problem, it proves the issue is at VDMA side.

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4 Replies
Scholar watari
Scholar
1,505 Views
Registered: ‎06-16-2013

Re: Synchronizing video signals with AXI4-Stream to Video

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Hi @emotal

 

I'm not sure. But your request seems how to design synchronizing video signal with genlock.

If yes, could you refer the following at page 16 to understand a methodology of genlock.

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf

 

Best regards,

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Visitor xlx
Visitor
1,438 Views
Registered: ‎03-01-2013

Re: Synchronizing video signals with AXI4-Stream to Video

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I use TPG to generate video source, this is AXI4-Stream for video pattern, you can test video too ! use ila to compare the diff!
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Xilinx Employee
Xilinx Employee
1,469 Views
Registered: ‎08-02-2007

Re: Synchronizing video signals with AXI4-Stream to Video

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@emotal

If the VtC timing matches the frame size from AXI4 Stream Video interface, it should be locked within a whole frame. if the SOF from VTC is too fast, it detects two sof from VTC, but no tuser from AXI4 Stream interface, it won't lock until you fix the frame size errors.

 

When you use it in master mode, it means VTC is timing master, in this case, it expects video stream coming from AXI4 Stream interface is free running, you can capture the Video Timing, Video AXI4 Stream interface in ILA, and check which is too fast, probably you need to slow down.

 

So the thing to check : 

1. HSize, Vsize register of VDMA read side, and see if it matches the settings in VTC

2. read side of VDMA is free run mode

 

As your Video stream is from VDMA, it could have SOF/EOL errors at read side at the beginning, you can double check this in the VDMA Status register at read side. If you do see error bits asserted, I think the problem is more at VDMA side rather than AXI4-Stream to Video Out side.

 

You can start with the test that contains VTG, VTC, AXI4-Stream to Video Out, if it doesn't have such problem, it proves the issue is at VDMA side.

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Highlighted
Moderator
Moderator
1,281 Views
Registered: ‎11-09-2015

Re: Synchronizing video signals with AXI4-Stream to Video

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Hi @emotal,

 

If everything is clear for you on this subject, please kindly mark a reply as solution to close the topic.

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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