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Adventurer
Adventurer
481 Views
Registered: ‎06-20-2019

Syntesis error due to MIPI CSI2 Tx Subsystem

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Hello everyone,

I am trying to synthesize a design which is actually a working one. However, I am unable to synthesize it right now.I have tried to reset output products and regenerate it many times. It seems as everything is updated. I am also able to run behavioral simulation. I am getting the folloiwng errors during synthesis:

[IP_Flow 19-3477] Update of parameter 'MODELPARAM_VALUE.C_DDR_CLK_PERIOD' failed for IP 'mipi_csi2_tx_subsystem_0/bd_6598/bd_6598_mipi_dphy_0_0'. can't use non-numeric string as operand of "+"

[IP_Flow 19-3428] Failed to create Customization object mipi_csi2_tx_subsystem_0/bd_6598/bd_6598_mipi_dphy_0_0

[IP_Flow 19-973] Failed to create IP instance 'bd_6598_mipi_dphy_0_0'. Error during customization.

[BD 41-1712] Create IP failed with errors

[BD 5-7] Error: running create_bd_cell -vlnv xilinx.com:ip:mipi_dphy:4.1 -type ip -name mipi_dphy_0 .

[IP_Flow 19-1747] Failed to deliver file '/tools/Xilinx/Vivado/2018.3/data/ip/xilinx/mipi_csi2_tx_subsystem_v2_0/elaborate/bd.xit': ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

[IP_Flow 19-167] Failed to deliver one or more file(s).

[IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'mipi_csi2_tx_subsystem_0'. Failed to generate 'Elaborate BD' outputs: Failed to elaborate IP.

[IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'mipi_csi2_tx_subsystem_0'. Failed to generate 'Elaborate BD' outputs: Failed to elaborate IP.

 

When I rerun the vivado, I sometimes get the following errors:

[Synth 8-439] module 'bd_6598_mipi_csi2_tx_ctrl_0_0' not found

[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

[Synth 8-439] module 'bd_6598_mipi_dphy_0_0' not found

[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

 

 

Thank you for your time.

 

 

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Xilinx Employee
Xilinx Employee
415 Views
Registered: ‎03-07-2018

Re: Syntesis error due to MIPI CSI2 Tx Subsystem

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Hello @yhy.xilinx 

After perfoming generate output products, I have synthesized MIPI TX example design in Vivado 2019.1.1 sucessfully.

MIPI TX EG Generate output products.png

MIPI TX EG Synthesized design.png

As you mentioned, earlier you were able to synthesize this example; but you are not able to synthesize this example currently. 

Please try steps below:

1. Create archive from your MIPI TX example project (keep all option unticked):

Project Archive 1.png

Project Archive 2.png

2. Extract this archive and try re-run above mentioned steps.

Other things to check:

1. Please check your system disk space is sufficient or not;

2, If you are in windows OS, please try to reduce directory path length of example design.

Regards,
Bhushan

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7 Replies
Xilinx Employee
Xilinx Employee
461 Views
Registered: ‎03-07-2018

Re: Syntesis error due to MIPI CSI2 Tx Subsystem

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Hello @yhy.xilinx 

MIPI CSI-2 TX example design is provided in PG260 for performing a simulation of MIPI CSI-2 Tx/Rx Subsystems and to understand the interface behavior. 

I do not think this can used for hardware implementation "AS IS".

I will run some test and let you know details.

Regards,
Bhushan

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Xilinx Employee
Xilinx Employee
441 Views
Registered: ‎03-30-2016

Re: Syntesis error due to MIPI CSI2 Tx Subsystem

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Hello @yhy.xilinx 
Just to give my two cents.

Do you have IP License for this MIPI CSI-2 TX Subsystem ?
If not please get some evaluation license for this IP.

Regards
Leo

XF_TX_LICENSE.jpg
Adventurer
Adventurer
432 Views
Registered: ‎06-20-2019

Re: Syntesis error due to MIPI CSI2 Tx Subsystem

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Hello @karnanl,

I have the license for the next 3 months and i am also checking it with vlm in order to see if it is detected by vivado.
Moderator
Moderator
425 Views
Registered: ‎11-09-2015

Re: Syntesis error due to MIPI CSI2 Tx Subsystem

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HI @yhy.xilinx 

Are you using a supported OS? Microsoft Windows 10.0 1809 Update; 10.0 1903 Pre-release (64-bit), English/Japanese

The language here is important. I have seen some similar issue with local not set with a supported language.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Xilinx Employee
Xilinx Employee
416 Views
Registered: ‎03-07-2018

Re: Syntesis error due to MIPI CSI2 Tx Subsystem

Jump to solution

Hello @yhy.xilinx 

After perfoming generate output products, I have synthesized MIPI TX example design in Vivado 2019.1.1 sucessfully.

MIPI TX EG Generate output products.png

MIPI TX EG Synthesized design.png

As you mentioned, earlier you were able to synthesize this example; but you are not able to synthesize this example currently. 

Please try steps below:

1. Create archive from your MIPI TX example project (keep all option unticked):

Project Archive 1.png

Project Archive 2.png

2. Extract this archive and try re-run above mentioned steps.

Other things to check:

1. Please check your system disk space is sufficient or not;

2, If you are in windows OS, please try to reduce directory path length of example design.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------

View solution in original post

Moderator
Moderator
361 Views
Registered: ‎11-21-2018

Re: Syntesis error due to MIPI CSI2 Tx Subsystem

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Hi @yhy.xilinx 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer afrifa
Observer
27 Views
Registered: ‎05-08-2019

Re: Syntesis error due to MIPI CSI2 Tx Subsystem

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Hello,

i am not sure if the suggested solutions helped you solve your problem.

I have experienced in recent times a similar challenge and i was able to solve it by setting up a clean utf-8 environment on my Linux computer.

Run a locales check with the "locale" program. Set the variables below as indicated below if it appears differently:

LANG=en_US.UTF-8

LANGUAGE=en_US.UTF-8

LC_ALL=en_US.UTF

 

Hope this helps.

BR, Afrifa