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Registered: ‎09-16-2007

System Generator error during "generate"

Hello everyone!
I have a SysGen 9.2 (60 eval), Matlab 2006a, and Xilinx ISE 9.2.01i and Xilinx ISE 9.1i (this one because FFT blocks cannot work under ISE 9.2 - that is the message I get).
I have tried to do the generate function from the System Generator block and during "Running netlister" process an error message is raised.
I am using FFT block in the design - at first it was FFT v4_1 but since it won't even start generate process with it, I have changed it to FFT v3_2.
The error I have received during netlister process is this one:
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: ERROR:coreutil - Temporary directory
   _xsd) created for XST synthesis cannot be removed at C:\.netlist\sysgen\masterScript18403.pl line 36571

Reported by:
I have tried to generate from another computer wich has SysGen 8.2 but it reported different, but still not so clear message:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: couldn't copy C:\MATLAB\R2006a\work\trajko\sysgen\coregen_WPsA/coregen_tmp/single_port_block_memory_virtex4_6_1_76f8f88bbe761e08.edn to C:\DOCUME~1\cejkova\LOCALS~1\Temp/sg_core_cache/single_port_block_memory_virtex4_6_1_76f8f88bbe761e08/single_port_block_memory_virtex4_6_1_76f8f88bbe761e08.edn at C:/MATLAB/R2006a/toolbox/xilinx/sysgen/scripts/SgGenerateCores.pm line 545, <FLIST> line 9
If anyone can help me with this I will be very graitful. By the way, the design uses DSP48 blocks and it is quite complex (around 60 DSP's + FFT). The implementation chip is set to be Virtex4SX25.
Thanks a lot in advance!
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3 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2007

Re: System Generator error during "generate"

This is a question that should be directed at the Xilinx Technical Support.  The fact that the netlister if failing to generate the design is somthing they can debug and file the approarite change requests against the sotfware to fix this issue.

You can open a case with the Xilinx Support by going here:
Video Design Hub | Embedded SW Support

Don’t forget to Reply, Kudo, and Accept as Solution.
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Visitor runningwild
Registered: ‎08-02-2007

Re: System Generator error during "generate"

Hi Miloss,

There seem to be a couple things going on here:

1. SysGen 9.2 is not supported with MATLAB 2006a (refer to AR 17966 for compatible versions).

2. The problem you are getting in SysGen 8.2 is probably being caused by spaces in your target path directory.  In 8.2 and older, spaces in the path are not allowed.

Hope this helps.
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Participant krunal_h_bhavsar
Registered: ‎09-21-2007

Re: System Generator error during "generate"

           I am also getting this kind of error when I am compiling it as HDL netlist or for hardware co-simulation in system generator 8.2. Even I have set target directory as C: thouth it gives same error. If you got it's solution please give me.
          Thank you,
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