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Explorer
Explorer
2,001 Views
Registered: ‎12-18-2014

TX-DPHY Start-Up Time too long!

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Hi,

I configured TX DPHY for 4 Lanes each 1.5Gbit/s on the ZCU102 Board. The start-up time according to MIPI D-PHY v4.0 PG202 document (page 44) is 2*LPX_TIME + HS_PREPARE_TIME + HS_ZERO_TIME + CDC_DELAY

Which should roughly be 300ns. 

In my design it is about 1120ns!

What might be the reason?

 

Thank you.

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1 Solution

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Xilinx Employee
Xilinx Employee
2,162 Views
Registered: ‎03-30-2016

Re: TX-DPHY Start-Up Time too long!

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Hello @sevenclock

I am glad to hear that you already know the cause.

BTW, there is no minimum time requirement for stopstate.

If stopstate=high , it means D-PHY IP is completed sending HS-TRAIL and minimum time-requirement for LP-11.

You can immediately assert txrequesths signal after stopstate=high to start HS packet.

Hope this helps.

 

Thanks,

Leo

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11 Replies
Moderator
Moderator
1,959 Views
Registered: ‎10-04-2017

Re: TX-DPHY Start-Up Time too long!

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Hi @sevenclock,

 

To clarify:

Are you running in Hardware or trying to simulate the design?

What are you using to measure the start-up time?

Are you measuring the start-up time as txrequesths to txreadyhs?

What is your txbyteclkhs frequency?

Is this in High-speed mode or Low-power?

 

-Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Explorer
Explorer
1,955 Views
Registered: ‎12-18-2014

Re: TX-DPHY Start-Up Time too long!

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Hi @samk 

the measurement is done on hardware for initiating only high speed transactions.

Actually i am snychronizing those signals to core_clk domain and viewing it with ila core.

I have a simple pattern generator which is initiating only hs transactions with gaps in between.

Yes, I am measuring the start-up time as txrequesths to txreadyhs!

Txbyteclkhs is roughly 188MHz!

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Explorer
Explorer
1,954 Views
Registered: ‎12-18-2014

Re: TX-DPHY Start-Up Time too long!

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I am aware of the period differences between core_clock and txbyteclkhs!
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Explorer
Explorer
1,949 Views
Registered: ‎12-18-2014

Re: TX-DPHY Start-Up Time too long!

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Clock lane is driven in non-continuous mode(same as data lanes)!
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Xilinx Employee
Xilinx Employee
1,941 Views
Registered: ‎03-30-2016

Re: TX-DPHY Start-Up Time too long!

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Hi,

Could you please check your MIPI IP INIT_DONE is asserted before you start txrequesths ?

 

Thanks

Leo

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Explorer
Explorer
1,935 Views
Registered: ‎12-18-2014

Re: TX-DPHY Start-Up Time too long!

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Init_done is asserted! 

 

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Xilinx Employee
Xilinx Employee
1,915 Views
Registered: ‎03-30-2016

Re: TX-DPHY Start-Up Time too long!

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Hello @sevenclock,

I cannot reproduce what you have reported here. ( around 250ns on default setting )
Could you please share your ILA waveform on PPI I/F ?


Please check also PG202 Chapter 3 Example 1.
If you assert txrequesths before your MIPI TX is ready to transmit a new data (please check stopstate=1 for every lane),
your txrequesths will be ignored, and valid only after stopstate=1.

 

Thanks
Leo

Xilinx Employee
Xilinx Employee
1,867 Views
Registered: ‎03-30-2016

Re: TX-DPHY Start-Up Time too long!

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Hello @sevenclock 

 

Did you solve your problem ?

If you can share your ILA, I can help check the waveform.

 

Thanks

Leo

 

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Explorer
Explorer
1,850 Views
Registered: ‎12-18-2014

Re: TX-DPHY Start-Up Time too long!

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Hi @karnanl

Thank you for you support.

I attached screenshot of the simulation...

The TX lanes are very long in stop state. 

In simulation its about 675 ns. Which equals about 13x lpx_periods. Is there a minimum "stop state" -time defined?

 

 

Best regards

tx dphy treq to trdy.JPG

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Xilinx Employee
Xilinx Employee
2,163 Views
Registered: ‎03-30-2016

Re: TX-DPHY Start-Up Time too long!

Jump to solution

Hello @sevenclock

I am glad to hear that you already know the cause.

BTW, there is no minimum time requirement for stopstate.

If stopstate=high , it means D-PHY IP is completed sending HS-TRAIL and minimum time-requirement for LP-11.

You can immediately assert txrequesths signal after stopstate=high to start HS packet.

Hope this helps.

 

Thanks,

Leo

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Explorer
Explorer
1,119 Views
Registered: ‎12-18-2014

Re: TX-DPHY Start-Up Time too long!

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Hi @karnanl,
I used to put both data and clock lane to stopstate. But for my application it should also work to have only data lane in stopstate therby reducing treq to tready time.

Thank you.

Best regards.
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