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Visitor gayanca
Visitor
2,605 Views
Registered: ‎07-20-2009

Taking multiple clock outputs

Hi

 

Are there are any means to get mutiple clock frequencies from FPGA, which runs on system clock?

 

Are there any blocks in XSG to achieve above directly?

 

Thanks in advance.  

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Xilinx Employee
Xilinx Employee
2,391 Views
Registered: ‎08-07-2007

Re: Taking multiple clock outputs

SysGen can support multiple sample rates which are all derived from one system clock.  It can also create designs which require multiple clock inputs running at any arbitrary rates relative to one another.

 

See the upsample and downsample blocks as well as the multiple subysystem generator token for details on each option.

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