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Adventurer
Adventurer
1,180 Views
Registered: ‎09-18-2017

Testbench for VDMA on vivado 2017.3

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Hello, dear FPGA enthusiasts!

 

Currently, I have been working with my OV7670 camera and can present it on an HDMI screen.

However, this was done without a simulation.

What I want to do right now is to use a TPG provided from Xlinix in my design and remove the OV7670 fully.

However, the problem is that I really don't know how to go next since I am using uB together with a VDMA and TPG.

I know that you can include the ELF file from the uB in order to simulate your design together with uB.

My question to you is where I can find C code for the TPG used in the nexys video board?

Is there any guidelines or documents that provide information on how I have to set up my design before I simulate AXI4 peripherals. 

Do I need to create my own testbench or is there testbench's out there that are already done?

Initially, I was using the ILA to test my peripherals but that is a very ineffective way of testing my models since it takes a lot of time and it is hectic to recompile when I make a small change.

I have attached my block design.

 

 

I have checked the https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf and found a testbench on page 68 Figure 5‐1 in the datasheet. However, there is no link that shows where you can get it.

 

Currently I have been downloading the following examples:

 

Xapp741- Could not open it though, complaining on "const is a hardware description language".

xapp742

xapp128_vdma

 

regards,

John

 

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Adventurer
Adventurer
1,599 Views
Registered: ‎09-18-2017

Re: Testbench for VDMA on vivado 2017.3

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Oh, I just had to press on "open IP example" when I place the VDMA example in my block design.

 

Thought I was suppose to get the example from the xapp_xxx examples provided by the page.

 

 

 

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Moderator
Moderator
1,139 Views
Registered: ‎11-09-2015

Re: Testbench for VDMA on vivado 2017.3

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Hi @azurath,

 

I know that you can include the ELF file from the uB in order to simulate your design together with uB

> A simpler case would be to use an AXI VIP to configure the registers. Else you might want to look at xapp1180.

 

I have checked the https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf and found a testbench on page 68 Figure 5‐1 in the datasheet. However, there is no link that shows where you can get it.

> The documentation is quite clear though. "Example Design Test Bench". And it is in the chapter Example design. So you just need to generate the example design as per section "Implementing the Example Design" and you will see it in the simulation sources.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
1,137 Views
Registered: ‎09-18-2017

Re: Testbench for VDMA on vivado 2017.3

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Hello Again @florentw!

Thanks for the info, guess I was very tired yesterday. I will dig into the datasheet and double check it.

 

Thanks, again.

 

regards,

John

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Adventurer
Adventurer
1,600 Views
Registered: ‎09-18-2017

Re: Testbench for VDMA on vivado 2017.3

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Oh, I just had to press on "open IP example" when I place the VDMA example in my block design.

 

Thought I was suppose to get the example from the xapp_xxx examples provided by the page.

 

 

 

0 Kudos