04-20-2012 05:35 AM
I was I wondering if you could tell me the structure of the adder in the DSP48A1, a Ripple carry adder, Kogge&Stone, Sklansky or other other kind of adders? Because I want to know whether it is possible for me to implement another adder with higher efficiency and more area consumption.
Thank you very much!
04-20-2012 07:44 AM
04-23-2012 12:05 AM
the DSP48xx blocks are pre implemented hard macros (like BRAMS too).
Their internal structure can not be changed. And since they are implemented directly in the silicon rather than using the FPGA LUT fabric, they are way faster than anything that could be done with LUTs (except if you are going for something beyond the DSP48's datawidth).
So the question about their internal structure is meaningless exept when you are a ASIC designer working on the next generation FPGAs. But these guys probably won't ask questions here in the forum.
For the rest of us it's some black box with defined properties. Maybe one can derive some hints about the internal structure by carefully reading the datasheet or doing some timing simulations.
There are other threads around in these forums concerning the effectiveness of different adder structures in FPGAs.
Due to the fast carry logic in the slices it's hard to beat the simple ripple adder architecture.
Have a nice synthesis