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Newbie adouraghy
Newbie
7,832 Views
Registered: ‎11-07-2007

Timing -- Period of the Constraint??

Anyone,
My SysGen model passes the timing analysis (No negative skew and the highest logic level is 19). TRACE reports 0 timing errors.
However, when trying to generate a bitstream it will fail at the very end.
Searching the details I find the following error:
 
WARNING:Timing:3232 - Timing Constraint
   "TS_RCH_RXCLK = PERIOD TIMEGRP "RCH_RXCLK" 2 ns HIGH 50%;"
    fails the minimum period check for clock U_top/u_custom_logic/u_sysgen/u_rch_rx_data_l/rxclk_sig because the period
   constraint value (2000 ps) is less than the minimum internal period limit of 4000 ps.   Please increase the period of
   the constraint to remove this timing failure.
 
Followed by:
 
Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.
 
------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors  
------------------------------------------------------------------------------------------------------
* TS_U_top_adac_dcm_clk_sig = PERIOD TIMEGR | 10.000ns   | 10.634ns   | 10     | -0.634ns   | 13     
  P "U_top_adac_dcm_clk_sig"         TS_ACQ |            |            |        |            |        
  UISITION_CLK HIGH 50%                     |            |            |        |            |        
------------------------------------------------------------------------------------------------------
 
It seems this is the only constraint holding up my design, but I have no idea how to solve it. If the solution is related to increasing the period of the constraint... how do I do that in SysGen?
Any help would be extremely appreciated. Thanks.
 
-Ali
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3 Replies
Xilinx Employee
Xilinx Employee
7,819 Views
Registered: ‎08-07-2007

Re: Timing -- Period of the Constraint??

This message is a warning and should not cause PAR or Bitgen to fail.  There may be another issue that is causing the failure.

To control the period constraint set by System Generator you need to modify the field titled "FPGA clock period (ns)" in the System Generator token.  If you are still having trouble with generating a bitstream please open a webcase with Xilinx Technical Support for further assistance on your specific design.
http://support.xilinx.com/support/clearexpress/websupport.htm
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Observer rubyt
Observer
7,812 Views
Registered: ‎08-14-2007

Re: Timing -- Period of the Constraint??

Hi adouraghy,

These warnings usually indicate that the period constraint specified in your design violates one of the Spec'ed operating ranges in the datasheet for that device (ie, faster than the Max Frequency of a DCM, etc.). This doesn't necessarily mean that it won't work, but it does mean that it's outside of the range that Xilinx has tested and guarantees. You might take a look in the datasheet for the device you're targetting to see if the frequency you're requesting is outside of the range for either it's driver or load.

rubyt
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Observer cbranson
Observer
7,723 Views
Registered: ‎09-12-2007

Re: Timing -- Period of the Constraint??

I've had the same problem.  But it DIDN'T let me PAR.
 
My solution was to just add in a few more delays in my data path that was causing the delay.  I don't think that System Generator does the timing right all the time.  Least that is my opinion... but I'm no expert.
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