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Visitor hoalenew
Visitor
1,091 Views
Registered: ‎04-18-2018

UHD-SDI 6G-SDI REFERENCE XAPP1249

Device: xc7z045iffg676-2L. Design using xapp1249 as reference. Configured as 6G-SDI, 4 data stream(ds1,ds2,ds3,ds4). The video pattern generator generated(Y data stream,C data stream). In the app said each copy of Y,C are sent to ds1-ds8 input of the Tx. Please explaint

How 4:2:2 YCbCr 10-bit image mapping per ST2081-10 mapping mode1 for transport on a 6G-SDI.

 

When I looked at the Fig3-11 6G-SDI TX 4-way interleave timing diagram on page 48 of PG205 document . and looked the SMPTE ST2081-10

SECTION 4.1.2  2160-line 40-bit virtual interace mapping on page 9 of 39 on the SMPTE ST 2801-10.

I don't understand how the mapping work. Please advise.

Hoa

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2007

Re: UHD-SDI 6G-SDI REFERENCE XAPP1249

The Xilinx UHD-SDI core does not be doing any packing.  It is delivering the elementary streams as they are received.  We leave all the packing up to the user.  The SMPTE UHD-SDI IP only does muxing (TX) or demuxing (RX) of the Data Streams to the 6G-SDI 10-bit interface as shown in Figure 3 of ST 2081-10.  We just do one extra layer of muxing or demuxing to separate out the elementary streams, (i.e luma (Y) and chroma (C)) that the Specification doesnt show.
 
For more information, look at the SMPTE UHD-SDI Product Guide PG 205, page 6 paragraphs 1-3.  These will explain the difference between elementary streams and multiplexed streams.
 
The 6G-SDI Specification support two modes of image mapping:

  • ST 2081-10 - Section 4 Mode 1 (4 sub-images being mapped to 8 elementary data streams) = PG205 Figure 3-10 8-way interleaving
  • ST 2081-10 - Section 5 Mode 2 (2 sub-images being mapped to 4 elementary data streams) = PG205 Figure 3-9 4-way interleaving

The portion of the specification on page 6 of 22 from ST 2081-10 is Mode 1 mapping, which is equivalent to PG205 Figure 3-10 for the UHD-SDI Rx core and PG205 Figure 3-12 for the UHD-SDI Tx core.  In the figures, the tx_ce is enabled every other clock cycle to allow for the muxing of the Y and C data onto the same stream, which results in the data stream patterns in the specification 4.1.2 2160-line 40-bit Virtual Interface Mapping (Informative).

The ST2081-10 Mode 2 mapping starts on page 11 of the specification and is equivalent to PG205 Figure 3-9 for the UHD-SDI Rx core and PG205 Figure 3-11 for the UHD-SDI Tx core.

Basically the SMPTE UHD-SDI core is parsing the incoming streams looking for the EAV and SAV and separating out the elementary streams based on these sequences.  You should be able to probe all 8 of the output data stream outputs from the SMPTE UHD-SDI Rx IP and that they either conform to PG205 Figure 3-9 for 4-way interleaved timing, or PG205 Figure 3-10 for 8-way interleaved timing.  You need to monitor not only the data stream interfaces, but also the rx_ce_out signal.

NOTE:  For UltraScale+ users they can also look at the UHD-SDI Rx Subsystems, which support both AXI4-Stream and Native SDI interfaces.  The Native Interface is basically the same as the UHD-SDI core as described above.

Chris
Video Design Hub | Embedded SW Support

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Visitor hoalenew
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Registered: ‎04-18-2018

Re: UHD-SDI 6G-SDI REFERENCE XAPP1249

Please confirm that we are properly understanding the ST2081-10 Specification and the PG205 for our application.

We are attempting to transmit 3840 x 2160 @ 30Hz.  From the ST2081-10 Specification Mode 1 Supports 3840x2160 @ 30Hz, Mode 2 does not support 3840 x 2160 @ 30Hz.

Due to this we believe that we need to use Mode 1 which is shown in figure 3-12 of PG205.  From the ST2081-10 Specification, the Image Mapping is shown figure 4  - Carriage of a 2160-line source image formats in a single-link 6G-SDI interface.  This shows how the pixels in the image are mapped to the Y/C busses of the PG205 interface.  We believe Figure 4 and paragraph 4.1.2  in the ST2081-10 Specification maps to the PG205 document as follows:

PG205 figure 3-12
Signal Name  ST2081-10 Reference Comments
tx_ds1_in Sub Image 1, Data Stream 1 Even Line Y, Pixel Y0, Y1, Y4, Y5,…
tx_ds2_in Sub Image 1, Data Stream 1 Even Line Cb,Cr, Pixel Cb0, Cr0, Cb2, Cr2,..* (We believe this should be Cb0, Cr0,Cb4,Cr4 )
tx_ds3_in Sub Image 2, Data Stream 2 Even Line Y, Pixel Y2, Y3, Y6, Y7,…
tx_ds4_in Sub Image 2, Data Stream 2 Even Line Cb,Cr, Pixel Cb1, Cr1, Cb3, Cr3,..* (We believe this should be Cb2, Cr2, Cb6, Cr6 )
tx_ds5_in Sub Image 3, Data Stream 3 Odd Line Y, Pixel Y0, Y1, Y4, Y5,…
tx_ds6_in Sub Image 3, Data Stream 3 Odd Line Cb,Cr, Pixel Cb0, Cr0, Cb2, Cr2,…* (We believe this should be Cb0, Cr0, Cb4, Cr4 )
tx_ds7_in Sub Image 4, Data Stream 4 Odd Line Y, Pixel Y2, Y3, Y6, Y7,…
tx_ds8_in Sub Image 4, Data Stream 4 Odd Line Cb,Cr, Pixel Cb1, Cr1, Cb3, Cr3, …* (We believe this should be Cb2, Cr2, Cb6, Cr6 )

* This seems to be inconsistent with PG205.  We believe that this bus index should match what is shown below in PG205,

Figure 3‐11: 6G-SDI TX 4-way Interleave Timing Diagram

not is what is specified in ST2081-10 Specification. 

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2007

Re: UHD-SDI 6G-SDI REFERENCE XAPP1249

This can be confusing, but the problem is how the 6G Specification is written.  In general, ST2081-10 is written in terms of multiplexed streams (i.e. the Y and Cb,Cr are already multiplexed together.)  Whereas the SMPTE UHD-SDI IP is using elementary streams which means that the Y and Cb,Cr are sent into the IP separately and multiplexed inside of the SMPTE UHD-SDI IP.

To be more specific, figure in the ST2081-10 labeled Carriage of 2160-line source image formats in a single-link 6G-SDI interface shows a multiplexed stream, which consists of 2 elementary streams (Y and Cb,Cr), for each sub-image.  Since each multiplexed stream consists of 2 elementary streams * 4 sub-images (4 * 2 = 8), this means that Mode 1 is actually 8-way Interleave.  If you look at PG205 Figure 3-12 6G-SDI TX 8-way Interleave Timing Diagram, you will see that it is showing 8 elementary streams which aligns with ST 20181 Mode 1.

NOTE: For more information on the differences between the elementary and multiplexed streams you can look at the SMPTE UHD-SDI Product Guide PG 205, page 6 paragraphs 1-3.

 

 

As you noted, you will need to use ST2081-10 Mode 1 to support 3840 x 2160 @ 30Hz.

 

Again your initial mapping is correct.  Y and Cb,CR map to the different elementary stream interfaces on the SMPTE UHD-SDI Tx.  The reason is that it is correct is due to the way the Sub Images are split.  Sub Image 1 and 2 are always the even lines while Sub-Image 3 and 4 are always the odd lines.  This is discussed in Section 4.1.2 2160-line 40-bit Virtual Interface Mapping.

 

tx_ds1_in Sub Image 1, Data Stream 1 Even Line Y,     Pixel Y0,  Y1,  Y4,  Y5,…
tx_ds2_in Sub Image 1, Data Stream 1 Even Line Cb,Cr, Pixel Cb0, Cr0, Cb2, Cr2,…


tx_ds3_in Sub Image 2, Data Stream 2 Even Line Y,     Pixel Y2,  Y3,  Y6,  Y7, …
tx_ds4_in Sub Image 2, Data Stream 2 Even Line Cb,Cr, Pixel Cb1, Cr1, Cb3, Cr3, …

 

tx_ds5_in Sub Image 3, Data Stream 3 Odd Line Y,     Pixel Y0,  Y1,  Y4,  Y5,…
tx_ds6_in Sub Image 3, Data Stream 3 Odd Line Cb,Cr, Pixel Cb0, Cr0, Cb2, Cr2,…

 

tx_ds7_in Sub Image 4, Data Stream 4 Odd Line Y,     Pixel Y2,  Y3,  Y6,  Y7,…
tx_ds8_in Sub Image 4, Data Stream 4 Odd Line Cb,Cr, Pixel Cb1, Cr1, Cb3, Cr3, …

 

 

You also mentioned Figure 3-11 6G-SDI TX 4-way Interleave Timing Diagram, but this is actually for ST 2081-10 Mode 2 and not applicable for your use case of sending 3480 x 2160 @ 30Hz.  Again this is due to the fact that the diagrams for Mode 2 are showing a an already multiplexed Y and Cb,Cr stream for each of he sub-images.

 

If you want to look at this in hardware, add Vivado ILAs to the input of the UHD-SDI Tx in XAPP1248 (or XAPP1249) and look at the data.

Chris
Video Design Hub | Embedded SW Support

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Moderator
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Registered: ‎11-09-2015

Re: UHD-SDI 6G-SDI REFERENCE XAPP1249

Hello @hoalenew,

 

This topic is still open and is waiting for you:

    If your question is answered or your issue is solved, please mark the response which helped as solution
    If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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