UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant baf2099
Participant
172 Views
Registered: ‎03-17-2017

UHD-SDI GT with TX only

I'm working on a design with a single SDI transmitter using the "SMPTE UHD-SDI TX SUBSYSTEM" and "UHD-SDI GT" cores. I have everything connected as required between the two cores, however the "UHD-SDI GT" core has many open connections for RX stuff I don't need. I was hoping the RX side of this core would get synthesized out and be a non-issue, but it seems this causes many critical warnings and eventually an error in implementation.

What is the best way to connect these uneeded ports up to avoid this issue and not waste resources?

Tags (3)
0 Kudos
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
127 Views
Registered: ‎03-30-2016

Re: UHD-SDI GT with TX only

Hello @baf2099 

UHD-SDI GT only support Duplex and RX-only data flow for now.
Please check PG290 appendix C.

I am not sure if TX only is implementable since the GUI does not support it ,
but other users may give you some good input if you can share the critical warnings from your design implementation.

Thanks & regards
Leo

FORUM_SDI_GT.png
Moderator
Moderator
105 Views
Registered: ‎11-09-2015

Re: UHD-SDI GT with TX only

HI @baf2099 ,

I would try to set up the UHD-SDI GT as full duplex and then connect all the RX input to 0 and check if the RX part is optimized0

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
45 Views
Registered: ‎11-09-2015

Re: UHD-SDI GT with TX only

HI @baf2099 ,

Do you have any update on this? Is everything clear for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos