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Visitor mehdi_ab
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395 Views
Registered: ‎07-18-2019

UHD-SDI rx & tx clocking scheme

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Hello,

my design shall instantiate 4 UHD capable SDI with independant RX and TX channels that are on the same bank on ZU7EV-2 platform and I found 3 clock scheme in xilinx documentation. As I do not understand all ins and outs I am a bit confused about which model to follow:

  1. pg205 and AR #72449 describe a clock scheme where 2 refence clocks are provided to GTH : 148.5 MHz for integer video clock rates and 148.35 for fractional video clock rates. Then TX and RX channels of GTH use clock selector and internal dividers to derive the appropriate clock frequency as needed.
    • UHD-SDI GT IP does not allow to select CPLL as a link PLL type as AR #72449 prescribes. So the only way is to use UltraScale FPGAs Transceivers Wizard to configure GTH and instantiate it as an RTL module, is that correct?
    • Is there an example design of Transceiver Control module?

  2. pg290's pass-through example design shows another clocking scheme where a stable 148.5 MHz reference clock is provided to RX GTH channel and TX GTH channel reference clock is generated by on-PCB clock generator based on UHD-SDI RX output clock.
    • In that case, to change UHD-SDI TX clock independently of RX channel, it is only feasible by reprogramming on-PCB generator in order to reproduce Table5-3 of pg290, is that correct?

  3. pg289's pass-through example uses PICXO module to generate fractional clock for TX channel, UHD-SDI and UHD-SDI GT IPs communicating through sideband buses and zync software selecting fractional or integer mode for TX channels.
    • Is it possible in that case to have fractional mode on RX channel?

Finally, what is the recommended clock scheme for my case, with completely independent RX and TX channels 12G capable SDI?

Thanks in advance,

Mehdi

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Visitor mehdi_ab
Visitor
297 Views
Registered: ‎07-18-2019

Re: UHD-SDI rx & tx clocking scheme

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Hi @florentw ,

Thank you for your answers. Please find my clarifications after your answers in the text below :


@florentw wrote:

HI @mehdi_ab 


@mehdi_ab wrote:

Hello,

my design shall instantiate 4 UHD capable SDI with independant RX and TX channels that are on the same bank on ZU7EV-2 platform and I found 3 clock scheme in xilinx documentation. As I do not understand all ins and outs I am a bit confused about which model to follow:

  1. pg205 and AR #72449 describe a clock scheme where 2 refence clocks are provided to GTH : 148.5 MHz for integer video clock rates and 148.35 for fractional video clock rates. Then TX and RX channels of GTH use clock selector and internal dividers to derive the appropriate clock frequency as needed.
    • UHD-SDI GT IP does not allow to select CPLL as a link PLL type as AR #72449 prescribes. So the only way is to use UltraScale FPGAs Transceivers Wizard to configure GTH and instantiate it as an RTL module, is that correct?
    • Is there an example design of Transceiver Control module?

      [Florent] - Not sure what you mean here. I can select CPLL on a ZCU102 design
      UHD.JPG
      And the AR recommends to use the CPLL for -2 devices
      [Mehdi] I actually got the same options only with vivado 2019.2 but not 2019.1 and 2018.3. Can you confirm?

  2. pg290's pass-through example design shows another clocking scheme where a stable 148.5 MHz reference clock is provided to RX GTH channel and TX GTH channel reference clock is generated by on-PCB clock generator based on UHD-SDI RX output clock.
    • In that case, to change UHD-SDI TX clock independently of RX channel, it is only feasible by reprogramming on-PCB generator in order to reproduce Table5-3 of pg290, is that correct?
      [Florent] - I assume you are talking about figure 5-8 which is showing the example desing on ZCU106. This is one use case. Note that the design is modified following AR#72449 (TX using CPLL). The PG needs to be updates.
      [Mehdi] yes and I think that figure 5-9 describes better the clock scheme
      This design can have truly independant TX and RX. Yes you need to reprogram the TX clock if you want to support fractionnal and non-fractionnal rate. This is not required for RX as the PPM for the QPLL on US+ is enough to receive fractionnal rates with a 148.5MHz clock

      [Mehdi] When you say that I "need to reprogram TX clock", are you actually meaning reprogramming si5328?

  3. pg289's pass-through example uses PICXO module to generate fractional clock for TX channel, UHD-SDI and UHD-SDI GT IPs communicating through sideband buses and zync software selecting fractional or integer mode for TX channels.
    • Is it possible in that case to have fractional mode on RX channel?
      [Florent] -  Yes. Refer to xapp1308 which talk about PICXO in more details:
      A fractional pre-scaler circuit to enable both 148.5 MHz and 148.5/1.001 MHz to be locked to any HSYNC reference clock

[Mehdi] Thanks for the link, it is very interesting.

Finally, what is the recommended clock scheme for my case, with completely independent RX and TX channels 12G capable SDI?

[Florent] - With PICXO you need to have TX. So you would need to have 2 clocks if you want to be truly independant. So the example design for the ZCU106 is what you want to look at

[Mehdi] Just to make sure I got it, when I run script vcu_sdirxtx_proj.tcl in vivado 2019.1 and open UHD-SDI GT re-customize IP screen I get the following gui:

zcu106-sdi_rxtx-uhd_sdi_gt_recustomize.JPG

 

I understand as both TX and RX are clocked by QPLL0. I would then need to update vivado with 2019.2 to get CPLL choice and select it for TX, is that correct?

 

Thanks in advance,

Mehdi


 


 

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Moderator
Moderator
328 Views
Registered: ‎11-09-2015

Re: UHD-SDI rx & tx clocking scheme

Jump to solution

HI @mehdi_ab 


@mehdi_ab wrote:

Hello,

my design shall instantiate 4 UHD capable SDI with independant RX and TX channels that are on the same bank on ZU7EV-2 platform and I found 3 clock scheme in xilinx documentation. As I do not understand all ins and outs I am a bit confused about which model to follow:

  1. pg205 and AR #72449 describe a clock scheme where 2 refence clocks are provided to GTH : 148.5 MHz for integer video clock rates and 148.35 for fractional video clock rates. Then TX and RX channels of GTH use clock selector and internal dividers to derive the appropriate clock frequency as needed.
    • UHD-SDI GT IP does not allow to select CPLL as a link PLL type as AR #72449 prescribes. So the only way is to use UltraScale FPGAs Transceivers Wizard to configure GTH and instantiate it as an RTL module, is that correct?
    • Is there an example design of Transceiver Control module?
      [Florent] - Not sure what you mean here. I can select CPLL on a ZCU102 design
      UHD.JPG
      And the AR recommends to use the CPLL for -2 devices
  2. pg290's pass-through example design shows another clocking scheme where a stable 148.5 MHz reference clock is provided to RX GTH channel and TX GTH channel reference clock is generated by on-PCB clock generator based on UHD-SDI RX output clock.
    • In that case, to change UHD-SDI TX clock independently of RX channel, it is only feasible by reprogramming on-PCB generator in order to reproduce Table5-3 of pg290, is that correct?
      [Florent] - I assume you are talking about figure 5-8 which is showing the example desing on ZCU106. This is one use case. Note that the design is modified following AR#72449 (TX using CPLL). The PG needs to be updates.
      This design can have truly independant TX and RX. Yes you need to reprogram the TX clock if you want to support fractionnal and non-fractionnal rate. This is not required for RX as the PPM for the QPLL on US+ is enough to receive fractionnal rates with a 148.5MHz clock
  3. pg289's pass-through example uses PICXO module to generate fractional clock for TX channel, UHD-SDI and UHD-SDI GT IPs communicating through sideband buses and zync software selecting fractional or integer mode for TX channels.
    • Is it possible in that case to have fractional mode on RX channel?
      [Florent] -  Yes. Refer to xapp1308 which talk about PICXO in more details:
      A fractional pre-scaler circuit to enable both 148.5 MHz and 148.5/1.001 MHz to be locked to any HSYNC reference clock

Finally, what is the recommended clock scheme for my case, with completely independent RX and TX channels 12G capable SDI?

[Florent] - With PICXO you need to have TX. So you would need to have 2 clocks if you want to be truly independant. So the example design for the ZCU106 is what you want to look at

Thanks in advance,

Mehdi


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor mehdi_ab
Visitor
298 Views
Registered: ‎07-18-2019

Re: UHD-SDI rx & tx clocking scheme

Jump to solution

Hi @florentw ,

Thank you for your answers. Please find my clarifications after your answers in the text below :


@florentw wrote:

HI @mehdi_ab 


@mehdi_ab wrote:

Hello,

my design shall instantiate 4 UHD capable SDI with independant RX and TX channels that are on the same bank on ZU7EV-2 platform and I found 3 clock scheme in xilinx documentation. As I do not understand all ins and outs I am a bit confused about which model to follow:

  1. pg205 and AR #72449 describe a clock scheme where 2 refence clocks are provided to GTH : 148.5 MHz for integer video clock rates and 148.35 for fractional video clock rates. Then TX and RX channels of GTH use clock selector and internal dividers to derive the appropriate clock frequency as needed.
    • UHD-SDI GT IP does not allow to select CPLL as a link PLL type as AR #72449 prescribes. So the only way is to use UltraScale FPGAs Transceivers Wizard to configure GTH and instantiate it as an RTL module, is that correct?
    • Is there an example design of Transceiver Control module?

      [Florent] - Not sure what you mean here. I can select CPLL on a ZCU102 design
      UHD.JPG
      And the AR recommends to use the CPLL for -2 devices
      [Mehdi] I actually got the same options only with vivado 2019.2 but not 2019.1 and 2018.3. Can you confirm?

  2. pg290's pass-through example design shows another clocking scheme where a stable 148.5 MHz reference clock is provided to RX GTH channel and TX GTH channel reference clock is generated by on-PCB clock generator based on UHD-SDI RX output clock.
    • In that case, to change UHD-SDI TX clock independently of RX channel, it is only feasible by reprogramming on-PCB generator in order to reproduce Table5-3 of pg290, is that correct?
      [Florent] - I assume you are talking about figure 5-8 which is showing the example desing on ZCU106. This is one use case. Note that the design is modified following AR#72449 (TX using CPLL). The PG needs to be updates.
      [Mehdi] yes and I think that figure 5-9 describes better the clock scheme
      This design can have truly independant TX and RX. Yes you need to reprogram the TX clock if you want to support fractionnal and non-fractionnal rate. This is not required for RX as the PPM for the QPLL on US+ is enough to receive fractionnal rates with a 148.5MHz clock

      [Mehdi] When you say that I "need to reprogram TX clock", are you actually meaning reprogramming si5328?

  3. pg289's pass-through example uses PICXO module to generate fractional clock for TX channel, UHD-SDI and UHD-SDI GT IPs communicating through sideband buses and zync software selecting fractional or integer mode for TX channels.
    • Is it possible in that case to have fractional mode on RX channel?
      [Florent] -  Yes. Refer to xapp1308 which talk about PICXO in more details:
      A fractional pre-scaler circuit to enable both 148.5 MHz and 148.5/1.001 MHz to be locked to any HSYNC reference clock

[Mehdi] Thanks for the link, it is very interesting.

Finally, what is the recommended clock scheme for my case, with completely independent RX and TX channels 12G capable SDI?

[Florent] - With PICXO you need to have TX. So you would need to have 2 clocks if you want to be truly independant. So the example design for the ZCU106 is what you want to look at

[Mehdi] Just to make sure I got it, when I run script vcu_sdirxtx_proj.tcl in vivado 2019.1 and open UHD-SDI GT re-customize IP screen I get the following gui:

zcu106-sdi_rxtx-uhd_sdi_gt_recustomize.JPG

 

I understand as both TX and RX are clocked by QPLL0. I would then need to update vivado with 2019.2 to get CPLL choice and select it for TX, is that correct?

 

Thanks in advance,

Mehdi


 


 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: UHD-SDI rx & tx clocking scheme

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@mehdi_ab wrote


[Mehdi] I actually got the same options only with vivado 2019.2 but not 2019.1 and 2018.3. Can you confirm?

[Florent] - You are right, this was changed in 2019.2

[Mehdi] When you say that I "need to reprogram TX clock", are you actually meaning reprogramming si5328?

[Florent] - Yes

[Mehdi] Just to make sure I got it, when I run script vcu_sdirxtx_proj.tcl in vivado 2019.1 and open UHD-SDI GT re-customize IP screen I get the following gui. I understand as both TX and RX are clocked by QPLL0. I would then need to update vivado with 2019.2 to get CPLL choice and select it for TX, is that correct?

[Florent] - Yes correct

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor mehdi_ab
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282 Views
Registered: ‎07-18-2019

Re: UHD-SDI rx & tx clocking scheme

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Ok thank you very much @florentw 

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Visitor mehdi_ab
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Registered: ‎07-18-2019

Re: UHD-SDI rx & tx clocking scheme

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I would just like to clarify the following point : you said "the PPM for the QPLL on US+ is enough to receive fractionnal rates with a 148.5MHz clock". But pg205 states in Chapter3 §Clocking/Serial Transceiver RX Reference Clocks:

"For 12G-SDI, the serial transceiver CDR does not support ±1250 ppm tolerance. The CDR
tolerance is reduced to ±200 ppm at 12G-SDI line rates. This requires different reference
clock frequencies to be used to receive 11.88 Gb/s and 11.88/1.001 Gb/s. Typically, the two
reference clock frequencies used are 148.5 MHz (to receive 11.88 Gb/s) and
148.5/1.001 MHz (to receive 11.88/1.001 Gb/s)."

So it seems that I do actually need both integer and fractional reference clocks for 12G SDI.

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Moderator
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Registered: ‎11-09-2015

Re: UHD-SDI rx & tx clocking scheme

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Hi @mehdi_ab 

You are right. Looking at the US+ datasheet, both US+ GTH and GTY have a 200 ppm tolerance for RX.

I based my reply on the ZCU106 path-through example design:

SDI.JPG

This is something I need to clarify with development


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor mehdi_ab
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Registered: ‎07-18-2019

Re: UHD-SDI rx & tx clocking scheme

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Ok, thank you, I'm looking forward to reading your findings

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