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1,608 Views
Registered: ‎04-03-2017

UHDSDI IP builds both RX and TX logic, but I only need RX

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I am working on a design that needs only the RX direction of the SMPTE UHD-SDI Xilinx IP block.

 

The chip is quite crowded and I am trying to save space.

 

Even though there is no connection to the input or output ports of the TX module, it is synthesized and not optimized away.

 

I can find no options for a unidirectional design in the IP generator.

 

ISE used to have problems with keeping unused logic. Is that still a problem in Vivado?

 

Thanks for any help.

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1 Solution

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Xilinx Employee
Xilinx Employee
1,556 Views
Registered: ‎12-02-2009

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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I connected tx ports to default values or 0 and able to see that 2016.4 Vivado optimizing the logic.

 

uhdsdi_v1_0 core as it is (project_txrx.xpr.zip):

CLB LUTs : 3843

CLB Registers : 3918

 

uhdsdi_v1_0 core that has RX ports & TX ports not used (project_rx_only.xpr.zip):

CLB LUTs : 1517

CLB Registers : 1912

 

By looking at the resource numbers, it is clear that tool optimized the logic.

 

So, review your design and connections. 

11 Replies
Explorer
Explorer
1,582 Views
Registered: ‎03-17-2011

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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Hell @jhatalsky_artel,

 

Are you using the IPI to develop your project?

Have you considered using the UHD SDI Receiver subsystem? (PG290)

this one is not bidirectional.

 

regards,

 

Sébastien.

--Sebastien
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1,574 Views
Registered: ‎04-03-2017

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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I am not using the IPI, but I would be happy to use it if it could save me some gates.

 

I do not see any SDI blocks in the IPI except for the same bidirectional block I see in the IP catalog.

 

Perhaps this block exists in later versions of Vivado. I am using Vivado 16.4

 

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Xilinx Employee
Xilinx Employee
1,560 Views
Registered: ‎12-02-2009

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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UHD SDI Receiver subsystem first release is 2017.3 Vivado, 

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Xilinx Employee
Xilinx Employee
1,558 Views
Registered: ‎12-02-2009

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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Ideally tool should optimize. Are you connecting clock & clock enables to the TX portion of the signals?

If so, can you tie to following value:

1'b1 to tx_rst;

3'b000 to tx_mode, tx_mux_pattern; 

1'b0 to tx_clk, tx_ce, tx_sd_ce, tx_edh_ce, tx_insert_crc, tx_insert_ln, tx_insert_st352, tx_insert_edh, tx_insert_sync_bit, tx_use_anc_in, tx_overwrite_st352;

 

Here are tx ports with tie-off values:

.tx_clk(1'b0), // input wire tx_clk
.tx_ce(1'b0), // input wire tx_ce
.tx_sd_ce(1'b0), // input wire tx_sd_ce
.tx_edh_ce(1'b0), // input wire tx_edh_ce
.tx_rst(1'b1), // input wire tx_rst
.tx_mode(3'b000), // input wire [2 : 0] tx_mode
.tx_insert_crc(1'b0), // input wire tx_insert_crc
.tx_insert_ln(1'b0), // input wire tx_insert_ln
.tx_insert_st352(1'b0), // input wire tx_insert_st352
.tx_overwrite_st352(1'b0), // input wire tx_overwrite_st352
.tx_insert_edh(1'b0), // input wire tx_insert_edh
.tx_mux_pattern(3'b000), // input wire [2 : 0] tx_mux_pattern
.tx_insert_sync_bit(1'b0), // input wire tx_insert_sync_bit
.tx_sd_bitrep_bypass(1'b0), // input wire tx_sd_bitrep_bypass
.tx_line_ch0('d0), // input wire [10 : 0] tx_line_ch0
.tx_line_ch1('d0), // input wire [10 : 0] tx_line_ch1
.tx_st352_line_f1('d0), // input wire [10 : 0] tx_st352_line_f1
.tx_st352_line_f2('d0), // input wire [10 : 0] tx_st352_line_f2
.tx_st352_f2_en(1'b0), // input wire tx_st352_f2_en
.tx_st352_data_ch0('d0), // input wire [31 : 0] tx_st352_data_ch0
.tx_st352_data_ch1('d0), // input wire [31 : 0] tx_st352_data_ch1
.tx_ds1_in('d0), // input wire [9 : 0] tx_ds1_in
.tx_ds2_in('d0), // input wire [9 : 0] tx_ds2_in
.tx_ds3_in('d0), // input wire [9 : 0] tx_ds3_in
.tx_ds4_in('d0), // input wire [9 : 0] tx_ds4_in
.tx_ds1_st352_out(), // output wire [9 : 0] tx_ds1_st352_out
.tx_ds2_st352_out(), // output wire [9 : 0] tx_ds2_st352_out
.tx_ds3_st352_out(), // output wire [9 : 0] tx_ds3_st352_out
.tx_ds4_st352_out(), // output wire [9 : 0] tx_ds4_st352_out
.tx_ds1_anc_in('d0), // input wire [9 : 0] tx_ds1_anc_in
.tx_ds2_anc_in('d0), // input wire [9 : 0] tx_ds2_anc_in
.tx_ds3_anc_in('d0), // input wire [9 : 0] tx_ds3_anc_in
.tx_ds4_anc_in('d0), // input wire [9 : 0] tx_ds4_anc_in
.tx_use_anc_in(1'b0), // input wire tx_use_anc_in
.tx_txdata(), // output wire [19 : 0] tx_txdata
.tx_ce_align_err() // output wire tx_ce_align_err

1,523 Views
Registered: ‎04-03-2017

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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That didn't work. I tried leaving all inputs floating, which also did not work.

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Xilinx Employee
Xilinx Employee
1,557 Views
Registered: ‎12-02-2009

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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I connected tx ports to default values or 0 and able to see that 2016.4 Vivado optimizing the logic.

 

uhdsdi_v1_0 core as it is (project_txrx.xpr.zip):

CLB LUTs : 3843

CLB Registers : 3918

 

uhdsdi_v1_0 core that has RX ports & TX ports not used (project_rx_only.xpr.zip):

CLB LUTs : 1517

CLB Registers : 1912

 

By looking at the resource numbers, it is clear that tool optimized the logic.

 

So, review your design and connections. 

Moderator
Moderator
1,458 Views
Registered: ‎11-09-2015

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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Hi @jhatalsky_artel,

 

Was the replies from @kka enough for you?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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1,445 Views
Registered: ‎04-03-2017

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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Is there a synthesis or optimization setting that controls removing unused logic? I have double checked my connections and they are what you requested that I do.

 

Have you looked at the implemented hierarchy to see if the TX block exists withing the UHDSDI block?

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Xilinx Employee
Xilinx Employee
1,442 Views
Registered: ‎12-02-2009

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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Both projects are attached in my last reply. Feel free to explore the hierarchy and share the results!

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1,035 Views
Registered: ‎04-03-2017

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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Finally, the TX block optimized away.

 

In your original instructions you said to put a zero on the control lines, but said nothing about the data paths (video, ancillary, line numbers), so I left them floating.

 

In your design you tied those lines to 0.

 

I don't know why that would make a difference, but when I tied data and control to 0 the tools were finally able to figure out that the module should be optimized away.

 

The problem is solved, thank you.

 

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Moderator
Moderator
1,021 Views
Registered: ‎11-09-2015

Re: UHDSDI IP builds both RX and TX logic, but I only need RX

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Hi @jhatalsky_artel,

 

As your issue is solved, please kindly mark the reply from kka which contains the answer as accepted solution (click on accept as solution). It can help other members who are experiencing the same issue.

 

You can also give kudos by clicking on the button with a star  kudos.PNG to thanks a user for its reply (it is free ;) ). You might want ot give also a kudos to @sebo who tried to help you.

 

Thanks and Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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