12-17-2018 01:18 AM
we use the 2lanes mipi tx dphy to light the 2lanes MIPI LCD
firstly use lane0 to send lpdt cmd ,have confirmed the cmd was right .when switch to high speed mode found that the clock lane and data lane1could enter into the high speed mode but the data lane0 could not ,by capture wave the clock lane and dlane1 wave is the same as spec request but the data lane0 not ,we doubt the LCD module 's not recgonize the cmd for diff Ths-settle time , so could you please give your suggest about xilinx demoed or verfied 2lane LCD ?
12-17-2018 04:35 PM
12-17-2018 06:08 PM
yes ,we use the LogiCORE MIPI D-PHY IP as tx ,lane data rate is 300mbps, two lanes capture wave could find in the attached file.
01-08-2019 02:56 AM
01-08-2019 04:54 PM
Hello Rocky @rockyzhang
Did you solve this issue ?
Xilinx has a working Application example design , that connect MIPI DSI TX to MIPI Display. (Please see PG232 Chapter 5). We do not use MIPI CSI-2 TX for LCD interoperability test.
If you want to set a lower settle time value, you have to check the "Enable AXI-4 Lite Register I/F" for D-PHY IP on your MIPI CSI-2 TX wizard GUI, and change the D-PHY IP HS_SETTLE register value (check PG202 for the detail address. Older IP has a common register to set all lanes, while 2018.3 IP has registers to control each lane)
You posted two oscilloscope screenshot, which one is data lane0 waveform ?
Thanks & regards
01-16-2019 06:15 AM
Do you have any update on this topic?
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Thanks and Regards,