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Visitor rockyzhang
Visitor
719 Views
Registered: ‎07-17-2017

UltraScale+ ZCU102 MIPI DHPY TX

we use the 2lanes mipi tx dphy to light the 2lanes MIPI LCD

      firstly use lane0 to send lpdt cmd ,have confirmed the cmd was right .when switch to high speed mode found that the clock lane and data lane1could enter into the high speed mode but the data lane0 could not ,by capture wave the clock lane and dlane1 wave is the same as spec request but the data lane0 not  ,we doubt the LCD module 's not recgonize the cmd for diff Ths-settle time , so could you please give your suggest about xilinx demoed or verfied 2lane LCD  ?

Thanks!!

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5 Replies
Xilinx Employee
Xilinx Employee
687 Views
Registered: ‎06-21-2018

Re: UltraScale+ ZCU102 MIPI DHPY TX

Hi rockyzhang,

Are you using the LogiCORE MIPI D-PHY IP?

If so, this might be of help:

https://www.xilinx.com/support/answers/54550.html

Thanks,

Andres

 

Visitor rockyzhang
Visitor
679 Views
Registered: ‎07-17-2017

Re: UltraScale+ ZCU102 MIPI DHPY TX

yes ,we use the LogiCORE MIPI D-PHY IP as tx ,lane data rate is 300mbps, two lanes capture wave could find in the attached file.

LP2HSdlan0.png
LP2HSdlan1.png
Xilinx Employee
Xilinx Employee
593 Views
Registered: ‎03-30-2016

Re: UltraScale+ ZCU102 MIPI DHPY TX

Hello @rockyzhang

Could you please send me your XCI file ? I need to check the IP version and configuration.
I cannot find the file on your post.

Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
576 Views
Registered: ‎03-30-2016

Re: UltraScale+ ZCU102 MIPI DHPY TX

Hello Rocky @rockyzhang

Did you solve this issue ?
Xilinx has a working Application example design , that connect MIPI DSI TX to MIPI Display. (Please see PG232 Chapter 5). We do not use MIPI CSI-2 TX for LCD interoperability test.

If you want to set a lower settle time value, you have to check the "Enable AXI-4 Lite Register I/F" for D-PHY IP on your MIPI CSI-2 TX wizard GUI, and change the D-PHY IP HS_SETTLE register value (check PG202 for the detail address. Older IP has a common register to set all lanes, while 2018.3 IP has registers to control each lane)

You posted two oscilloscope screenshot, which one is data lane0 waveform ?

Thanks & regards
Leo

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Moderator
Moderator
498 Views
Registered: ‎11-09-2015

Re: UltraScale+ ZCU102 MIPI DHPY TX

HI @rockyzhang,

Do you have any update on this topic?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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