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Adventurer
Adventurer
262 Views
Registered: ‎09-03-2015

Ultrascale Pin Assignement bitslice

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Hello Guys,

I want to instantiate the Xilinx MIPI D-Phy Ip core and i have questions about the Pin Assignement. See the attached picture.

I'm wondering if i can do the pinning in this way. The wizard complains about it. But if i synthesize and implement the design in Vivado 2018.2, it

builds without any errors or critical warnings.

I think the Problem is that i don't assign the Pins continuously.

The D-Phy document says:

-select the IO pins continuously without leaving any IO pairs in the middle of D-PHY interface.

-PHY IP uses IO in Native mode. Left out IO cannot be used by any other design and it willbe unusable.

 

Lets make a look on my pinning again.

The clock is assigned to T3L_N0 and the first Data Lane to T3U_N6.

Does it mean, that i cannont use the pinns between them? So in my case Data Lane1 (T3L_N4) and Data Lane3 (T3L_N2) are not usable?

So it won't work in that way right?

So why does vivado build the implementation without any errors or warnings?

I'm using the device: xczu7eg-fbvb900

 

Thank you very much

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mipi_pinout.PNG
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1 Solution

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Xilinx Employee
Xilinx Employee
173 Views
Registered: ‎03-30-2016

Re: Ultrascale Pin Assignement bitslice

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Hello @astei87


>I think the Problem is that i don't assign the Pins continuously.

Yes. Your understanding is correct.
Current MIPI IP suggested to assign all pin continously without leaving any IO pairs in the middle
, because we might have some unusable bg*_pin*_nc pins.
So, the DRC implemented in the MIPI GUI is only check whether the pins are continuously assigned or not.
Please note that this is a warning message, not an error message.

If you already implemented your test design, and Vivado says it is okay, then your pin-assignment is correct.

>Does it mean, that i cannont use the pinns between them? So in my case Data Lane1 (T3L_N4) and Data Lane3 (T3L_N2) are not usable?

No. It is usable.
All pins are in the same nibble. Looks good.


>So why does vivado build the implementation without any errors or warnings?

Because your pin assignment is correct.
--Current MIPI GUI DRC only check for the pin-assignment continuity.

Thanks & regards
Leo

 

2 Replies
Xilinx Employee
Xilinx Employee
174 Views
Registered: ‎03-30-2016

Re: Ultrascale Pin Assignement bitslice

Jump to solution

Hello @astei87


>I think the Problem is that i don't assign the Pins continuously.

Yes. Your understanding is correct.
Current MIPI IP suggested to assign all pin continously without leaving any IO pairs in the middle
, because we might have some unusable bg*_pin*_nc pins.
So, the DRC implemented in the MIPI GUI is only check whether the pins are continuously assigned or not.
Please note that this is a warning message, not an error message.

If you already implemented your test design, and Vivado says it is okay, then your pin-assignment is correct.

>Does it mean, that i cannont use the pinns between them? So in my case Data Lane1 (T3L_N4) and Data Lane3 (T3L_N2) are not usable?

No. It is usable.
All pins are in the same nibble. Looks good.


>So why does vivado build the implementation without any errors or warnings?

Because your pin assignment is correct.
--Current MIPI GUI DRC only check for the pin-assignment continuity.

Thanks & regards
Leo

 

Adventurer
Adventurer
161 Views
Registered: ‎09-03-2015

Re: Ultrascale Pin Assignement bitslice

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All right,

thank you very much :)

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