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Participant dave74321
Participant
1,845 Views
Registered: ‎09-29-2016

Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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Progressive video frames in the AXI stream need to be outputted as interlaced video fields to drive a PAL/NTSC composite video encoder. i.e. 1 frame converted to 2 interlaced fields

 

With the video frames written to a frame buffer in SDRAM using the AXI VDMA LogiCORE, it then needs to read the frame out of the frame buffer and send 1st,3rd,5th...lines and then read the same frame again and send 2nd,4th,6th...lines

 

Is there a simply way to force the AXI VDMA LogiCORE to always read the same frame twice?

(And to always read the frame an even number of times until the next frame is ready to be read)

 

Thanks

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Participant dave74321
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2,254 Views
Registered: ‎09-29-2016

Re: Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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To the question “Is there a simply way to force the AXI VDMA LogiCORE to always read the same frame twice?”

Answer “no, not simply”.

 

 

This has been simulated and seems to work fine (not tried in hardware)

 

AXI stream:

  • Input 12.5 progressive frames per second
  • Output 50 interlaced fields per second (25 frames per second)

 

i.e. generally every frame read 4 times out of the frame store:

  • Odd field (from frame 1), Even field (from frame 1), Odd field (from frame 1), Even field (from frame 1)

then

  • Odd field (from frame 2), Even field (from frame 2), Odd field (from frame 2), Even field (from frame 2)

Etc

 

Create custom logic to:

  • Generate a field_id signal (toggles when mm2s_fsync_out pulses)
  • Assign VDMA read frame pointer (s2mm_frame_ptr_out copied to mm2s_frame_ptr_in every 2 fields. Note the VDMA samples mm2s_frame_ptr_in when it generates fsync_out)
  • Discard odd or even lines depending on field_id (remembering to add back in a Start of Frame on the tuser when one has been discarded)

 

VDMA Core configured as:

  • 3 Frame buffers
  • Wr fsync: s3mm tuser
  • Wr GenLock: Dynamic-Master
  • Rd fsync: None
  • Rd GenLock: Dynamic-Slave

 

VDMA i/o made visible with TCL commands:

  • mm2s_frame_ptr_in: set_property -dict [list CONFIG.c_mm2s_genlock_num_masters {2}] [get_bd_cells axi_vdma_0]
  • mm2s_fsync_out: set_property -dict [list CONFIG.c_enable_mm2s_fsync_out {1}] [get_bd_cells axi_vdma_0]

 

VDMA registers set as:

  • Addr x"00000030" value x"0000008b"-- S2MM internal master 1
  • Addr x"00000000" value x"0000010b"-- MM2S external master 2
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Moderator
Moderator
1,801 Views
Registered: ‎11-09-2015

Re: Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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Hi @dave74321,

 

From the VDMA configuration register:

VDMA.PNG

 

You might want to investigate this parameter.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor xlx
Visitor
1,781 Views
Registered: ‎03-01-2013

Re: Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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I think video to read out by Progressive, use to generate_pll 1/2 Clk to drive videoout odd-frame odd line and even-frame even line . VTC Control the Video timing.
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Participant dave74321
Participant
1,743 Views
Registered: ‎09-29-2016

Re: Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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I would like the interlacing under Programming Logic rather than Processing System control.  Therefore I have not attempted to use the configuration register “Circular_Park”.

 

I am currently creating logic to monitor the VDMA s2mm_frame_ptr_out and mm2s_introut and drive mm2s_frame_ptr_in so that it outputs the appropriate frame twice.  

 

 

VDMA as dynamic-master write (frame sync to tuser) and dynamic-slave read.  mm2s_frame_ptr_in is made available using tcl command:

set_property -dict [list CONFIG.c_mm2s_genlock_num_masters {2}] [get_bd_cells axi_vdma_0]

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Explorer
Explorer
1,734 Views
Registered: ‎07-18-2011

Re: Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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Are you interlacing a 30Hz progressive video frame input into two 60Hz interlaced fields, or a 60Hz progressive video frame input into two 60Hz interlaced fields?

 

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Participant dave74321
Participant
1,726 Views
Registered: ‎09-29-2016

Re: Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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Input is 12.5 progressive frames per second

Output is 50 interlaced fields per second (25 frames per second)

 

i.e. generally every frame will be read 4 times out of the frame store:

Odd field (from frame 1), Even field (from frame 1), Odd field (from frame 1), Even field (from frame 1)

then

Odd field (from frame 2), Even field (from frame 2), Odd field (from frame 2), Even field (from frame 2)

etc

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Moderator
Moderator
1,642 Views
Registered: ‎11-09-2015

Re: Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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Hi @dave74321,

 

Did you make any progress on your custom logic?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant dave74321
Participant
2,255 Views
Registered: ‎09-29-2016

Re: Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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To the question “Is there a simply way to force the AXI VDMA LogiCORE to always read the same frame twice?”

Answer “no, not simply”.

 

 

This has been simulated and seems to work fine (not tried in hardware)

 

AXI stream:

  • Input 12.5 progressive frames per second
  • Output 50 interlaced fields per second (25 frames per second)

 

i.e. generally every frame read 4 times out of the frame store:

  • Odd field (from frame 1), Even field (from frame 1), Odd field (from frame 1), Even field (from frame 1)

then

  • Odd field (from frame 2), Even field (from frame 2), Odd field (from frame 2), Even field (from frame 2)

Etc

 

Create custom logic to:

  • Generate a field_id signal (toggles when mm2s_fsync_out pulses)
  • Assign VDMA read frame pointer (s2mm_frame_ptr_out copied to mm2s_frame_ptr_in every 2 fields. Note the VDMA samples mm2s_frame_ptr_in when it generates fsync_out)
  • Discard odd or even lines depending on field_id (remembering to add back in a Start of Frame on the tuser when one has been discarded)

 

VDMA Core configured as:

  • 3 Frame buffers
  • Wr fsync: s3mm tuser
  • Wr GenLock: Dynamic-Master
  • Rd fsync: None
  • Rd GenLock: Dynamic-Slave

 

VDMA i/o made visible with TCL commands:

  • mm2s_frame_ptr_in: set_property -dict [list CONFIG.c_mm2s_genlock_num_masters {2}] [get_bd_cells axi_vdma_0]
  • mm2s_fsync_out: set_property -dict [list CONFIG.c_enable_mm2s_fsync_out {1}] [get_bd_cells axi_vdma_0]

 

VDMA registers set as:

  • Addr x"00000030" value x"0000008b"-- S2MM internal master 1
  • Addr x"00000000" value x"0000010b"-- MM2S external master 2
Explorer
Explorer
1,474 Views
Registered: ‎07-18-2011

Re: Using AXI VDMA LogiCORE to convert progressive video to interlaced video

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@dave74321   A few points for your consideration:

 

(1) If you simply decimate the frame to create two fields without vertically pre-filtering the video, you will get flicker in the output image if there is a sharp vertical transition in the input image.  For example, if you have a single white horizontal line in your input image, it will show up in one field in the output, but not in the next.  This will create a noticeable flicker at the output field rate.

 

(2) If you are forcing a fixed, synchronous read/write of 4:1 in hardware, i.e., reading the same image four times for every one write, you are going to have to lock the output video clock and frame rate the to that of the input image.   This will prevent any possibility of frame synchronization if the input and output frames don't match.   For example, since you mentioned the possibility of doing NTSC,  if your input image is 15Hz (one-fourth of 60Hz), and you want to output NTSC to a BT.656 encoder at the standard 29.97Hz frame rate for 720x480i, it wouldn't work, because you would periodically cross over your read/write frames due to the 29.97/30 frame rate difference, and you will see a mix of old/new data in the same output field.

 

(3) The easy way to read every other line from a VDMA is to set the stride equal to twice the line length, then reload the VDMA starting address at the top of each field to alternately start on the first line or the second line of the frame.   This can be done in several ways, but if you want to do it in hardware only, you might try configuring the VDMA via a coefficient file loaded into an AXI traffic generator IP block.  You can instantiate two traffic generators and enable them alternately by simply resetting the unused one alternately.  Use an AXI interconnect to tie them all into the VDMA.   Configure each VDMA to stop at the end of a transfer. The reset will reload the VDMA and initiate a new transfer.   I have used this in applications where a MicroBlaze was not allowed, and it worked fine to reconfigure the same VDMA in multiple ways, but I have never tried it for on-the-fly output side VDMA changes every frame, so you may have to experiment with it a bit.   I know the re-configuration occurs very quickly after a reset.

 

Should you decide to try this, following is an example of how to write the coefficient files for a VDMA.  There are two files, one for the address, and one for the data:   The NOPS at the end are to pad the length to 16, as set in the traffic generator.   Be sure to set the address (0x44A0nnnn in this case) to match your VDMA.

 

;VDMA address initialization file - 16 entries, must end in FFFFFFFF
memory_initialization_radix=16;
memory_initialization_vector=
;
;Addresses
;
;S2MM_VDMACR
44A00030
;S2MM_START_ADDRESS_1
44A000AC
;S2MM_START_ADDRESS_2
44A000B0
;S2MM_START_ADDRESS_3
44A000B4
;S2MM_FRMDLY_STRIDE    - note: in bytes, not pixels!
44A000A8
;S2MM_HSIZE, in bytes - note: bytes per line, not pixels!
44A000A4
;S2MM_VSIZE, in lines - note: must be written last
44A000A0
;
;NOPS
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF

 

;VDMA data initialization file - 16 entries, must end in FFFFFFFF
memory_initialization_radix=16;
memory_initialization_vector=
;
;Data
;
;S2MM_VDMACR
0000000B
;S2MM_START_ADDRESS_1
80000000
;S2MM_START_ADDRESS_2
80500000
;S2MM_START_ADDRESS_3
80A00000
;S2MM_FRMDLY_STRIDE    - note: in bytes, not pixels!
01001068
;S2MM_HSIZE, in bytes - note: bytes per line, not pixels!  1400 pixels/line * 3 bytes/pixel = 4200 bytes/line = 0x1068
00001068
;S2MM_VSIZE, in lines - note: must be written last
0000041A
;
;NOPS
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF

 

 

(4) The best way to accomplish what you are trying to do, with both vertical filtering to reduce flicker and frame synchronization to allow asynchronous input/output timing, is to configure your VDMA as you would normally for progressive-scan input and output images, using a triple-buffer with the write side set as master and the read side set as slave.  Configure the read side to follow the write with a 1 frame delay, and it will drop or repeat frames as necessary to stay there.   This will accomplish the frame synchronization.

 

Next, write a custom interlacer IP block to generate an interlaced image at half the clock rate of the input image.  This is easily done by using two FIFOs configured as 1H line buffers to make a three-tap vertical filter, with coefficients of  [0.25, 0.5, 0.25].   You can do this either in the AXI4-Stream domain, or after the AXI4-to-Video IP block before your output video encoder interface IP.  I assume you are using some BT.656-type format encoder, such as the Analog Devices ADV7391, which will require colorspace and chroma resampling IP to convert your RGB 4:4:4 image to Y/CrCb 4:2:2.   If so, it is easiest to do the interlacer prior to the chroma resampling just to make the data line up easier, if you have plenty of resources to spare and don't need the absolute smallest solution.

 

The only tricky part with the inline video interlacer is that you need to average up in one field, and down in the next, but this can be done by controlling the 1H FIFO reads appropriately at the start of each frame.   For example, field one should average lines x,1,2, to generate output line 1, then lines 2, 3, 4 to generate line 2, then lines 4, 5, 6 to generate line 3, etc.  Field two should average lines 1,2,3 to generate output line 1, then lines 3,4,5 to generate output line 2, then lines 5,6,7 to generate output line 3, etc.  

 

You have to be careful with the beginning and ending lines, since there is no data on one of the lines for each field.  In practice, this is not particularly noticeable if you average with zero for the first line of field one and the last line of field two, it just creates a slightly lower luminance line at the top of field one and the bottom of field two. Be sure to reset your 1H FIFOs at the beginning of each field, and hold off the transfer of  data from the first FIFO to the second until 1H of data has been written to the first, then enable both to write on each valid pixel.

 

I have successfully designed and implemented this type of video interlacer IP and can vouch for it's quality compared to scan-line decimation.   For further reading on non-interlaced to interlaced video conversion, I highly recommend purchasing a copy of Keith Jack's excellent book "Video Demystified", fifth edition.  It has a section on this very subject.