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Contributor
Contributor
318 Views
Registered: ‎02-08-2018

Using Video Processing Sub system IP Core

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Hello,

 I am trying to convert Bayer RAW data into YUV 4:2:0 ,So that i am using Sensor Demosaic and video processing subsystem IP core .    

I have created design for convert bayer to YUV 4:2:0 using Sensor Demosaic IP(Bayer to RGB) and Video Processing Subsystem(RGB to YUV 4:2:0). My design is worked till Sensor Demosaic IP, Here i got RGB converted data but after using Video processing subsystem (Customization used as shown in file Vpss_IP.jpg) and IP external connection shown in Vpss_ip_connection.jpg).The problem is Video processing subsystem configuration is not happening.So if i am doing anything wrong in Designing(PL) please guide me to solve this issue. 

Vpss_IP.jpg
Vpss_ip_connection.jpg
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Moderator
Moderator
221 Views
Registered: ‎11-09-2015

Re: Using Video Processing Sub system IP Core

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Hi @nishith.kumar 

Few comments:

  • Make sure you are using the correct color format. For the output stream it should be XVIDC_CSF_YCRCB_420. Refer to the example application (which is the one you used as startimg point)
  • Then if you follow the function XSys_SetStreamParam, you will see that it tries to get a timing format from the height and the width you give it. But the resolution you give it is not a format available in the driver (check Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers\video_common_v4_5\src\xvidc_timings_table.c) thus it would fail. you need to create the custom resolution.

The second point is probably your issue. But note that you could have investigated by yourself printing the journal in the log as mentioned in my previous message. Please thy this function next time


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
274 Views
Registered: ‎11-09-2015

Re: Using Video Processing Sub system IP Core

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HI @nishith.kumar ,

I do not see anything wrong with the design. But how are you configuring the VPSS?

Just a reminder that direct access to the register is not supported for the VPSS. Only the configuration using the driver APIs is supported.

Can you share the code you are using to start the VPSS? Also it would help to have the UART log showing the journal feature of the VPSS.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
247 Views
Registered: ‎02-08-2018

Re: Using Video Processing Sub system IP Core

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Hi @florentw 

                  Please find below attached source files to configure VPSS.

 

Thanks and Regards

Nishith

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Moderator
Moderator
222 Views
Registered: ‎11-09-2015

Re: Using Video Processing Sub system IP Core

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Hi @nishith.kumar 

Few comments:

  • Make sure you are using the correct color format. For the output stream it should be XVIDC_CSF_YCRCB_420. Refer to the example application (which is the one you used as startimg point)
  • Then if you follow the function XSys_SetStreamParam, you will see that it tries to get a timing format from the height and the width you give it. But the resolution you give it is not a format available in the driver (check Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers\video_common_v4_5\src\xvidc_timings_table.c) thus it would fail. you need to create the custom resolution.

The second point is probably your issue. But note that you could have investigated by yourself printing the journal in the log as mentioned in my previous message. Please thy this function next time


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
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Registered: ‎02-08-2018

Re: Using Video Processing Sub system IP Core

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Hi @florentw ,

 

We have done changes in code as you said , i want to clarify that earlier we were using SCALER ONLY but now now we are using COLOR SPACE CONVERSION, so now we are able to receive image test pattern(Reference_Pattern.jpg) all the way from sensor to vpss till vdma buffers, we can see pattern(as shown in attatched file 10.bin). but we want to know the data formation in memory . how YUV420 data will be organized in memory which is Output of VPSS. so as per microsoft documents we referred data will be stored like Y from starting index to width*height then from there U till the index(width*height/4) and V is also same as U.

 

Please help to know this concept because i want to read Y,U&V components individually to compress data using JPEG encoder.

Reference_Pattern.jpg
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Moderator
Moderator
173 Views
Registered: ‎11-09-2015

Re: Using Video Processing Sub system IP Core

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Hi @nishith.kumar ,

Since your original question is now solved, please kindly close the topic by marking my previous reply, which gave you the answer, as accepted solution to close the topic (please keep one topic = one question).

Then for you second question you might want ot read my video series and specifically my video series 9 and video series 10. If this is still unclear (even if the answer are in the previous link) please create a new topic.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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