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Voyager
Voyager
1,151 Views
Registered: ‎02-01-2013

VCU reference clock requirement

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PG252 indicates that the reference clock for the VCU should come from an external source:

RefClkReqt1.jpg

 

RefClkReqt2.jpg

 

However, when I run Block Automation on a VCU that I've added, it creates (by default) a reference clock from a PS-generated clock:

AutoConnectedRefClk.jpg

 

It does this instead of creating an external port for the reference clock, as it does for the MIG's reference clock.

 

I also see that the VCU TRD (which I don't have) is intended to run on the ZCU106 board--but I can't find a suitable external clock reference on that board which the VCU might use. 

 

So I'm getting mixed signals here, and I'm uncertain of the clock requirement for the VCU's Reference Clock. 

 

-Joe G.

 

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Moderator
Moderator
1,164 Views
Registered: ‎10-04-2017

Re: VCU reference clock requirement

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Hi @jg_bds,

 

As @sebo@ mentioned, theTRD can be used as a guide.

 

In general, the product guide takes precedence. In this case, take a look at the most recent PG252 released June 6th.

 

2018-07-23 09_51_05-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

 

Regards,

Sam

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Xilinx Video Design Hub
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Explorer
Explorer
1,092 Views
Registered: ‎03-17-2011

Re: VCU reference clock requirement

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Hello @jg_bds,

 

This is indeed strange.

What I can tell you, is  that VCU TRD is using an external input clock (SYS_CLK):

set_property PACKAGE_PIN AH12 [get_ports SYSCLK_300_P]
set_property PACKAGE_PIN AJ12 [get_ports SYSCLK_300_N]

On the board, it is connected to a Si570 PLL. 300 MHz is it's default value.

 

That clock is running at 300Mhz and feed an internal PLL with 3 output clock.

The clk_out3 is the reference clock for the VCU and set to 33.333 MHZ.

 

Regards,

 

Sébastien.

--Sebastien
Moderator
Moderator
1,165 Views
Registered: ‎10-04-2017

Re: VCU reference clock requirement

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Hi @jg_bds,

 

As @sebo@ mentioned, theTRD can be used as a guide.

 

In general, the product guide takes precedence. In this case, take a look at the most recent PG252 released June 6th.

 

2018-07-23 09_51_05-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

 

Regards,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
Voyager
Voyager
1,062 Views
Registered: ‎02-01-2013

Re: VCU reference clock requirement

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@sebo, @samk:

 

Thank you for the replies. I'm now planning on tapping-off an external, 300-MHz, DDR reference clock and feeding it to the VCU after a divide-by-6 trip through a BUFGCE_DIV.

 

 

 

Explorer
Explorer
1,042 Views
Registered: ‎03-17-2011

Re: VCU reference clock requirement

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@jg_bds,

 

I'd try to run a simple implementation on the ZCU106 first in order to validate your idea.

-Sébastien.

--Sebastien
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