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Adventurer
Adventurer
1,172 Views
Registered: ‎09-21-2016

VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

Hello Everyone,

I am working with simple design to implement an image processing algorithm using Vivado HLS. I am using Zybo board. Vivado Hlx: 2016.4, HLS: 2016.4, SDK: 2015.4

The design works like the following diagram:

design.png

I take the input of the image file as a C file. In the debug mode, I save the memory data into a text file then reconstruct the output image by MATLAB.

I think my HLS image filter is working fine. But its one iteration latency is too high. Currently, it is 80 clock cycle. Anyway, the output is fine as I am sending only one image. But there is a line in my image. I cannot find the reason why may this happen.

result.jpg

my SDK code:

int main(){

	Xil_ICacheEnable();
	Xil_DCacheEnable();

	VDMA_Initalize (&Image_Vdma,VDMA0_Device_ID);
	inittestIp(); // initialize my HLS IP

	xil_printf("Initialization done\n");

	xil_printf("Write address: 0x%X\n",Image_DDR_write_MEMORY_offset);

	Image_MemInit();

	Image_VDMA_read_Setup (&Image_Vdma);
	xil_printf("read set up done\n");

	VDMA_write_setup(&Image_Vdma);
	xil_printf("write set up done\n");

	XTest_ip3_Start(&testIp); // start my HLS IP

	Xil_DCacheDisable();


	return 0;
}

 

I have followed some questions and answers thread in the forum. One of them focused on the disabling the data cache (Xil_DcacheDisable()). What is the importance of this function in the VDMA operation? Any useful study material will also be helpful.

My main questions are two:

  1. What are the possible reasons for the generation of this line?
  2. What is the importance of Data cache (enable/disable) in my design?

Any comments or useful study link will be very helpful. If you need to any other things about my design, please let me know.

 

Thank you

Rappy Saha.

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9 Replies
Moderator
Moderator
1,126 Views
Registered: ‎11-09-2015

Re: VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

Hi @rappysaha,

 

Did you check your HLS IP output in co-simulation? I do not think this is coming from the VDMA. You might want to add an ILA at the output of your HLS IP to see if the values are expected


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Adventurer
Adventurer
1,090 Views
Registered: ‎09-21-2016

Re: VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

Hi @florentw,

Sorry for late reply. Basically, I was investing the reason. I got the reason finally. But, I am still wondering why this thing will happen. The image width and height of the fish image is 482x375. The height is an odd number here. I gave input this image to my design. But in the debugging mode when I was reading the output, I read out only the 482x374. And there was no angular line. For debugging I used the following command:

 

set logfile [open "<directory location>\\log_zynq.txt" "w"]

puts $logfile [mrd  0x6EEC00 540804 b] // 482x375x3 = 542250 & 482x374x3 = 540804

close $logfile

 

As I was giving the input 482x375 but reading only 482x374, I think the problem is related to the readout in the debugging mode. My question is why in readout this problem will happen?

Any kind of idea or study link will be very appreciated.

Thank you

Rappy Saha

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Moderator
Moderator
1,067 Views
Registered: ‎11-09-2015

Re: VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

Hi @rappysaha,

 

Is the debug file capturing the output after your HLS IP or after the VDMA?

 

I think you might want to ask the question on the simulation board as it seems to be a simulation question


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
1,062 Views
Registered: ‎09-21-2016

Re: VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

Hello @florentw,

 

This debugging procedure is after my HLS IP. 

 

Previously, I said that when I changed the width and height of the image in even number the problem was gone. Currently, I am again having the same problem even though the width and height of the image in even number. I am surely missing something. I will investigate more about it. And I will surely post about it on Simulation and Verification by referencing this post.

 

Thank you

Rappy Saha

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Moderator
Moderator
1,018 Views
Registered: ‎11-09-2015

Re: VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

HI @rappysaha,

 

Did you verified the behaviour of your IP inside HLS before exporting it to vivado?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
999 Views
Registered: ‎09-21-2016

Re: VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

Hello @florentw,

I am very sorry for late reply. 

 

Surely, I have examined my C-simulation in the HLS and it was working nicely. In the co-simulation method, I have verified the signals from the scope. But, I am not sure how to verify by with image in the co-simulation stage. 

 

I researched further about this matter. What I have found that for some resolutions (eg. 240x320), everything is working fine when for some resolutions (e.g. 483x375) it is not working. I am having angular lines in that case. I know it sounds strange. But the fact is I am still trying to find the reason. 

 

Thank you

Rappy Saha

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Moderator
Moderator
995 Views
Registered: ‎11-09-2015

Re: VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

HI @rappysaha,

 

I am not HSL expert but I believe you can take the same test bench for co-simulation. HLS just change the design under test to the RTL fonction


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
987 Views
Registered: ‎09-21-2016

Re: VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

Hi @florentw,

 

I understand totally. HLS can take the same test bench to the Co-simulation. And my co-simulation passed successfully. But what I want to say, in C-simulation I can see the image directly, where I did not find any angular line for any image. In case of co-simulation, I cannot see the image directly. 

 

Anyway, I will search more about this verification. 

 

Thank you

Rappy Saha

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Moderator
Moderator
887 Views
Registered: ‎11-09-2015

Re: VDMA 6.2 to HLS Image IP to VDMA 6.2 : cannot have proper output image

Hi @rappysaha,

 

Do you have nay updates on this?

If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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