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1,145 Views
Registered: ‎10-09-2017

VDMA Width Conversion

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For optimizing throughput through the VDMA, I need to reduce the clock rate of the streaming AXI bus to be lower than the memory-mapped AXI bus.

 

I must change a 220MHz 32-bit streaming AXI bus into a 110MHz 64-bit bus. I need this clock and width conversion in both the S2MM and MM2S directions.

 

Can either the AXI width conversion or the AXI streaming interconnect perform this clock and width conversion and still maintain the correct TLAST and TUSER signaling for video syncs?

 

Thanks!

John

 

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Registered: ‎10-09-2017

Re: VDMA Width Conversion

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Hi samk,

 

Thanks for the reply.

 

To answer your question, I am running the streaming VDMA at 110MHz with a 64-bit data bus. It was originally a 32-bit data bus running at 220MHz, but I changed it so that the streaming clock rate would be lower than the memory mapped clock rate for optimal throughput.

 

I did try to force the IPI tool to automatically propagate my settings to the AXI interfaces in my design, but the tuser signal was still never generated at the output of the AXI streaming interconnect. My design requires usage of tuser as video sync, so I was forced to abandon usage of the AXI streaming interconnect in the design.

 

The AXI data width converter would not work for my either because it does not do the clock conversion that I needed. In the end, I created my own custom AXI clock and width converter and that worked great.

 

Thanks!

John

 

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Registered: ‎10-04-2017

Re: VDMA Width Conversion

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Hi jlevieux@a2etechnologies.com,

 

For optimizing throughput through the VDMA, I need to reduce the clock rate of the streaming AXI bus to be lower than the memory-mapped AXI bus.

 

The VDMA does not need to be run asynchronously to be optimized.

Here are rough throughput limitations of the core in synchronous and asynchronous mode.

 

Synchronous mode:
(AXI4-Stream bus width * common clock * bus efficiency)  or

(AXI4 bus width *common clock * bus efficiency)

Whichever is smaller.


In Asynchronous mode, width conversion is done using the AXI4 clock. This means that the throughput is now constrained by:

(AXI4-Stream bus width * AXI4-Stream clock * bus efficiency)  or

(AXI4 bus width * AXI4 clock * bus efficiency)  or

(AXI4-Stream bus width * AXI4 clock )

Whichever is smaller.

 

I must change a 220MHz 32-bit streaming AXI bus into a 110MHz 64-bit bus. I need this clock and width conversion in both the S2MM and MM2S directions.

The VDMA should be able to do these conversions as long as the bandwidth is large enough to handle the video stream. Is there a reason you need to convert the bus width outside of the VDMA?

 

Can either the AXI width conversion or the AXI streaming interconnect perform this clock and width conversion and still maintain the correct TLAST and TUSER signaling for video syncs

Xilinx video converted into the AXI Stream format should be compatible with the AXI stream library.

 

For more information please take a look at:

PG035

PG085

PG020

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Xilinx Video Design Hub
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Registered: ‎10-04-2017

Re: VDMA Width Conversion

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Hi jlevieux@a2etechnologies.com,

 

The VDMA does not need to be run asynchronously to be optimized.

 

Here are rough throughput limitations of the core in synchronous and asynchronous mode.

Synchronous mode:
(AXI4-Stream bus width * common clock * bus efficiency)  or

(AXI4 bus width *common clock * bus efficiency)

whichever is smaller.


In Asynchronous mode, width conversion is done using the AXI4 clock. This means that if the throughput is now constrained by:

(AXI4-Stream bus width * AXI4-Stream clock * bus efficiency)  or

(AXI4 bus width * AXI4 clock * bus efficiency)  or

(AXI4-Stream bus width * AXI4 clock )

Whichever is smaller.

 

I must change a 220MHz 32-bit streaming AXI bus into a 110MHz 64-bit bus. I need this clock and width conversion in both the S2MM and MM2S directions.

The VDMA should be able to do these conversions without an issue. Is there a reason you need to convert the bus width outside of the VDMA?

 

Can either the AXI width conversion or the AXI streaming interconnect perform this clock and width conversion and still maintain the correct TLAST and TUSER signaling for video syncs?

Xilinx video converted into the AXI Stream format should be compatible with the AXI stream library.

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Registered: ‎10-09-2017

Re: VDMA Width Conversion

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Hi Samk,

 

Thanks for the reply. 

 

1. Yes, there is a reason I need to convert the bus width outside of the VDMA. It is because I need to increase my streaming AXI bus width in order to compensate for reducing my streaming AXI clock rate which is necessary to make the streaming AXI clock rate lower than the AXI memory mapped clock rate. The lower streaming clock rate is taking into account the note below in the VDMA product guide PG020:

 

"IMPORTANT: Make sure the memory map side clock frequency is equal to or greater than the
streaming side clock frequency to achieve required performance."

 

2. I tried to get the AXI streaming interconnect configured to support the AXI signal generating TUSER at the output. I could make the IP core support TUSER on the input, but none of the IP configuration settings in IP Integrator and nothing in the product guide PG085 allowed support of TUSER at the ouput. Is it possible to add this TUSER support to the IP block?

 

Thanks for your help!

John

 

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Registered: ‎10-04-2017

Re: VDMA Width Conversion

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Hi jlevieux@a2etechnologies.com,

 

 

1. I believe the following note is there to make sure that throughput considerations are taken into consideration for the core. Failing to do so can result in backpressure starting from the memory interface.


"IMPORTANT: Make sure the memory map side clock frequency is equal to or greater than the
streaming side clock frequency to achieve required performance."

 

Dividing the frequency by two, but multiplying the bus width by two will have a negligible effect on throughput. 

Q1. What are you running the AXI4 clock at and what is the width of the AXI4 bus width?

If you are running the memory interface at 110MHz with a 32-bit bus, you will have an issue. However, you should be fine running the memory interface at 110Mhz with a 64-bit bus. *I have not tested this, but from a throughput perspective, I do not see an issue.

 

2. In IPI most of the AXI interfaces are handled automatically. You will need to connect the interfaces then select validate design to get the automatic interfaces to generate. The tool does not constantly run the design propagation, or it would take up too many resources.

 

I do not believe that there is a use case where you would use the AXI4-Stream interconnect to do width conversion. The AXI4-Stream Data Width Converter is better suited for this. That being said, you should not need either of these in your design as the VDMA has width conversion built-in.

 

Please let me know if you are successful and I will submit a request to change "frequency" to "throughput" in the documentation.

 

-Sam

 

 

 

 

 

 

 

 

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Registered: ‎10-09-2017

Re: VDMA Width Conversion

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Hi samk,

 

Thanks for the reply.

 

To answer your question, I am running the streaming VDMA at 110MHz with a 64-bit data bus. It was originally a 32-bit data bus running at 220MHz, but I changed it so that the streaming clock rate would be lower than the memory mapped clock rate for optimal throughput.

 

I did try to force the IPI tool to automatically propagate my settings to the AXI interfaces in my design, but the tuser signal was still never generated at the output of the AXI streaming interconnect. My design requires usage of tuser as video sync, so I was forced to abandon usage of the AXI streaming interconnect in the design.

 

The AXI data width converter would not work for my either because it does not do the clock conversion that I needed. In the end, I created my own custom AXI clock and width converter and that worked great.

 

Thanks!

John

 

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