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Observer petercaddick
Observer
101 Views
Registered: ‎04-01-2019

VDMA addressing

Hi 

I have a design with multiple VDMAs. As a result I've had to use the GP port for one of the vdmas.When I do this the address map is as per the attachment. However the GP1_M_AXI_GP0 doesn't get assigned an address and I get a warning. The vdma is only connected to the M_AXI port and it connects to GP1. Should I assign GP1_M_AXI_GP0 an address? If I don't what are the consequencies? Also I need to ensure that all the vdmas aren't using the same space in the DDR. This is done entirely in the software configuration and if thats wrong I will see corruption. Is that correct? Also is there some were that reports what DDR address space is being used? 

Tags (2)
vdma_addressing_1.jpg
vdma_addressing_2.jpg
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2 Replies
Xilinx Employee
Xilinx Employee
73 Views
Registered: ‎11-21-2018

Re: VDMA addressing

Hi Peter,

Would you be able to send me your design so I can replicate it on my end and get a better understanding of your issue?

Regards,
Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Xilinx Employee
Xilinx Employee
25 Views
Registered: ‎11-21-2018

Re: VDMA addressing

Hi @petercaddick 

 

I think I was able to reproduce your issue. Were you receiving the following warning? 

Forum1.PNG

If this is the warning then you do not need to worry about it because your design should still work as expected. However, I think the way you have setup the system is not as efficent as it could be so I included some recommendations below: 

  • Is there a specific reason why you are using he GP ports? There are 4 HPM ports available which would be quicker than using the GP ports. Are you using all 4 of these already? More information about the HPM ports is in UG585 pg55.Forum2.PNG
  • Did you check the BW requirement for both VDMA? Could they share HPM interfaces (using interconnect)? The estimate throughput for HPM interfaces is 1200MB/s per interface.

 

Regards, 

Aoife 

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**