10-28-2016 11:07 AM
I have achieved getting interlaced data in and out of the VDMA and have my video being displayed via my SDI output. However the video seems to jump back and forth from the even and odd fields being in the right order to not being in the right order. I say this because the video runs for awhile and looks good and then edges start getting jagged and lines appear between text on a sheet of tilted paper,etc, for awhile and then pops back into normal. I have the VDMA set up for Master write and Slave read. I have 4 frame buffers and the frame delay set to 4, which I thought would take care of the issue of the buffers getting out of sync from my FID generation (which I took from the vid_interlacer_v1_0 example design). Any suggestions?
10-31-2016 06:37 AM
Is what I am trying to do possible. In PG020 it states for Genlock slave : "When configured as Genlock Slave, the channel tries to catch up with the Genlock Master either by skipping or repeating frames"
This in my mind seems to conflict with the Genlock Master statement : "Genlock Slave should
follow the Genlock Master with a predetermined frame delay value set in its *frmdly_stride[28:24]."
My Vivado Analyze captures of the output frame pointers seem to indicate that the Genlock master statement about frame delay is not being adhered to,
11-25-2016 01:47 AM
As discussed in the SR,
Transfering interlaced video between two different clock domains will create issues with field ordering .A CR has been filed with development to improve the documentation of the product guides AXIStoVideoOUT and VideoIN to AXIS IP regarding interlaced operation support.