08-24-2016 01:57 PM - edited 08-25-2016 05:41 AM
There's something with a AXI VDMA that I can not explain (the AXI Video-in aclk, VDMA srteamIN and streamOUT use the same clock source 25.2MHz, which is higher that the vid_io_in_clk 20MHz, no unaligned allowed for VDMA setting, write - dynamic master, read - dynamic slave). I use VDMA read and write interrupts to count how many frames were written and read from memory.
When input stream data-width is set to 24bit and output stream data-width is 24 bits everything seems to work, memory read and write ratio is relative to the external video in (20) and out (25.2) clocks: 20/25.2 = 47/59.
Then, keeping everything unchanged, when I change the data widths on input and output to 8bit and 8bit respectively, my VDMA memory write/read ratio changes, however, the clocks are the same: 20/25.2 != 94/39 Moreover, I get some garbage reading, or at least I think so. Why does this happen?