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Contributor
Contributor
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Registered: ‎05-10-2019

VDMA data packing for S2MM case where Stream side is 16 bit and Memory side is 64 bit

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Hi,

 

I am using VDMA to transfer video data from CSI2 Rx to DDR.

For CSI2 I have chosen One pixel per beat for RAW12 format and Video format bridge is enabled.

So, on Streaming interface from CSI2 to VDMA, the data width is 16. (4'X, Pixel data =12 bit)

On VDMA Master interface the data width is 64.

My question is how does VDMA transfer data on these 64 bits

Is it going to be

64 bit data =   [4'X, Pixel3, 4'X, Pixel2, 4'X Pixel1, 4'X Pixel0]

or 

64 bit data =  [16'x, Pixel3, Pixel 2, Pixel1, Pixel 0]

I am also trying to simulate the block but any input from the forum will be helpful

 

 

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Moderator
Moderator
408 Views
Registered: ‎10-04-2017

Re: VDMA data packing for S2MM case where Stream side is 16 bit and Memory side is 64 bit

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Hi @bhanu27,

 

The VDMA is not configured to work in specific formats. This is shown by no mention of RAW/YUV/RGB formats in PG020.

Because the VDMA does not know the format, it does not know that you are sending pixels in the format of 4'X,PIXEL on a clock basis. It only sees that it gets valid 16bits of pixel data every clock that it needs to write into memory.


Because of this, I am making the assumption that the data transfer will not separate out the 4X(unknown bits) from each transfer.

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

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2 Replies
Moderator
Moderator
409 Views
Registered: ‎10-04-2017

Re: VDMA data packing for S2MM case where Stream side is 16 bit and Memory side is 64 bit

Jump to solution

Hi @bhanu27,

 

The VDMA is not configured to work in specific formats. This is shown by no mention of RAW/YUV/RGB formats in PG020.

Because the VDMA does not know the format, it does not know that you are sending pixels in the format of 4'X,PIXEL on a clock basis. It only sees that it gets valid 16bits of pixel data every clock that it needs to write into memory.


Because of this, I am making the assumption that the data transfer will not separate out the 4X(unknown bits) from each transfer.

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

Moderator
Moderator
369 Views
Registered: ‎11-09-2015

Re: VDMA data packing for S2MM case where Stream side is 16 bit and Memory side is 64 bit

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Hi @bhanu27 

Is everything clear for you? Was @samk 's reply enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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