UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor omar-xilinx
Visitor
798 Views
Registered: ‎12-07-2017

VDMA using issues

Hi,

I'm actually struggling to get the  VDMA works on my video processing bloc diagram.

First, I reproduced Digilent's workshop Digilent Zybo Workshop "ZYBO Video Workshop" simple HDMI in VGA out with a Sobel IP core made in Vivado HLS and it worked well. I used a fixed resolution of 1280x720p with a 60 fps from the HDMI source.

Then, I wanted to add a VDMA to store and read frames through the HP port of the Zynq processor, so I followed Digilent Zybo HDMI In but I didn't want to use the DynClk IP core because I'm actually using a fixed resolution of 128x720p, and I used one VTC IP instead of two VTC. 

I saw on the VDMA user guide that it can operate on asynchronous and synchronous clocking mode, but only asynchronous mode is available. It also mentions that we have to use a Memory Map clock grater or equal to Streaming clock and that the Axi Lite clock of the VDMA should be less than or equal to the other clocks.

So I put,

Axi_Lite clock = 50Mhz

Core Clock scaler = 200 Mhz, only for DVi2RGB Digilent IP core

Fclk_Clk1 = 74.2 Mhz (I suppose that it's the fequency that I should use with a 1280x720p resolution)

There is also the pixel_clk generated from the DVi2RGB Digilent IP core that I think it is 100 Mhz ( accroding to the warnings and the error reports that I got).

For the configuration of the VDMA IP core, I put

Adress width 32

Stream Data width ( for read and write) 24

Line buffer depth 512

Frame buffer 3

Genlock mode (for writing) Dynamic-Master
Genlock mode ( for reading) Dynamic-Slave

When I generated the bitsream I got timing issues, with a Total Negative Slack of 7310 ns. So I tried to lower the frequncy Axi_Stream_Clock in order to avoir timing issues but still doen't work.

I also used to vdma_api to make the VDMA works on the SDK in triple buffer mode.

But still getting a Black Screen at the output.

I saw on a Xilinx forum that we should configure the Axi Stream to Video out IP core to get a Master Clock and disconnect its vtg_ce pin.

 For the clocking of the VDMA IP core:

I connected the MM side clocks(m_axi_mm2s_aclk and m_axi_s2mm_aclk) on Fclk_Clk1 = 74.2 Mhz.

I connected the Streaming side clocks (m_axis_mm2s_aclk and s_axis_s2mm_aclk) to the Pixel_Clk generated from the output of the DVI2RGB Digilent IP core and I think that Pixel_Clk = 100 Mhz.

I also checked the VTC configuration  to work in 1280x720p.

This is my SDK code.

 

/*** Include file ***/
#include "xparameters.h"
#include "xstatus.h"
#include "xaxivdma.h"
#include "xaxivdma_i.h"
#include "vdma_api.h"

#ifdef XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
#define MEMORY_BASE		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
#elif XPAR_MIG7SERIES_0_BASEADDR
#define MEMORY_BASE	XPAR_MIG7SERIES_0_BASEADDR
#elif XPAR_MIG_0_BASEADDR
#define MEMORY_BASE	XPAR_MIG_0_BASEADDR
#elif XPAR_PSU_DDR_0_S_AXI_BASEADDR
#define MEMORY_BASE	XPAR_PSU_DDR_0_S_AXI_BASEADDR
#else
#define MEMORY_BASE		0x01000000
#endif


/*** Global Variables ***/
unsigned int srcBuffer = (MEMORY_BASE  + 0x1000000);



#define DEBUG_MODE		0



int main()
{
	int Status;
	XAxiVdma InstancePtr;

	xil_printf("\n--- Entering main() --- \r\n");
	xil_printf("Starting  VDMA \n\r");

	/* Calling the API to configure and start VDMA without frame counter interrupt */
		Status = run_triple_frame_buffer(&InstancePtr, 0, 1280, 720,
							srcBuffer, 100, 0);
		if (Status != XST_SUCCESS) {
			xil_printf("Transfer of frames failed with error = %d\r\n",Status);
			return XST_FAILURE;
		} else {
			xil_printf("Transfer of frames started \r\n");
		}
    return 0;
}

 

The following pictures shows how i connected the clocks.

Pixel_Clk.pngPixel Clk from DVI2RGB Digilent IP core
200mhz.jpg200Mhz clock for the DVI2RGB Digilent IP coreLite.jpgAXI lite clock = 50 MhzMM.jpgMM side clock = 74.2 Mhzslack.jpgTotal Negative Salck of 7310 ns

 

 

0 Kudos
5 Replies
Moderator
Moderator
737 Views
Registered: ‎11-09-2015

Re: VDMA using issues

Hi @omar-xilinx 

For the timing violation with the VDMA, you are probably facing the issue mentioned in AR#71984.

Please refer to the AR for the constraints to add to your project to solve this.

Then you need to understand what is not working for your design:

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Moderator
Moderator
709 Views
Registered: ‎11-09-2015

Re: VDMA using issues

HI @omar-xilinx ,

Do you have any update on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Visitor omar-xilinx
Visitor
648 Views
Registered: ‎12-07-2017

Re: VDMA using issues

Hello Florent,  sorry for being so late to reply, I had a lot of things to do at the same time.

Thank you so much for your help. 

I'm still having troubles to get the VDMA works. First, I added the constraints part mentionned in AR#71984 like shown on the following picture.Constraints_Modif.pngConstraints added from AR#71984

Then I changed the MM clock to be greater than the Stream Clock. The following picture shows how I connect the MM side clocks and the Stream side clocks.VDMA_Clocking.png

I wanted to make a testbench for checking the output signals of the AXI-4 Stream to Video Out IP core, but it's not an easy task for me to give the right stimulus for all the signals.

After generating the bitstream and exporting it to the SDK, I check the S2MM and MM2S registers like you mentionned in Video Series 25: Debugging issues on the AXI VDMA IP. I noticed that I was wrong on the Hsize value, so I corrected it ( number of colums * number of bytes in one pixel). After that I got the following values for both the S2MM and MM2S  registers:   0x00010001, which means that the channel is Halted in the two directions.

So I checked your video series 25 and I modified the linker script and the base adress of the first Buffer like shown on the following pictures. But after that, I still get the same value of the two registers 0x00010001. Linker_Script.png

 

 

 

 

 

This is my SDK code and the Vivado Adress Editor.Vivado_Adress_Editor.png

SDK_Code.pngSDK code

0 Kudos
Moderator
Moderator
611 Views
Registered: ‎11-09-2015

Re: VDMA using issues

Hi @omar-xilinx 

  1. Did the constraints solved the timing issues in vivado? If you are still failing timing you need to solve this first
  2. What do you get on the UART console?
  3. How are you checking? The example will only run for 100 frames. So maybe by the time you are reading the register, it has read/written all the frames. Then it bis halted as expected. I would recommend using the same code as mine...

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Moderator
Moderator
540 Views
Registered: ‎11-09-2015

Re: VDMA using issues

Hi @omar-xilinx 

Do you have any update on this?

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos