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Contributor
Contributor
870 Views
Registered: ‎05-11-2018

VPSS Scaler Only with Native Video Input and Output

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I need use the VPSS Scaler Only IP to scale 4K 60Hz (4PPC) to 1080P 60Hz (4PPC).  My input video and output video (due to other design blocks) must be native video (RGB 4ppc). Eventually the entire design will consist of HDMI RX (native 4K@60Hz) => (our design block in native) => Video In to AXI Stream => VPSS(scaler only) => AXI Stream to Video Out (1080P@60Hz) => DDR3 Memory Interface => 1080P@120Hz => HDMI TX (native).

 

Currently I am just trying to get HDMI RX (native 4K@60Hz) => Video In to AXI Stream => VPSS(scaler only) => AXI Stream to Video Out (1080P@60Hz) => HDMI TX (native).

 

I have looked at xapp1285 and I am curious as to why it has a memory interface.  Do I need a frame buffer to be able to use the VPSS Scaler Only?  I have seen other postings that imply otherwise.  Could I remove the VDMAs from this example design and thus hook the TPG and/or Video In to AXI stream directly to the AXI Stream to Video Out block and it work just fine?

 

I decided with my own implementation to start with

 

HDMI RX (native 1080P@60Hz 4PPC) => Video In to AXI Stream => AXI Stream to Video Out (1080P@60Hz 4PPC) => HDMI TX (native).

 

to see if I can just get 1080P to pass through.  I have a VTC with detection disabled and generation enabled and hooked up to the AXI to Video Out block (slave mode).  Should this be in master mode?  Do I need detection enabled?  If so, why?  If I turn on detection I would assume this information is not used unless you enable synchronization.  If I enable synchronization it adds and fsync_in to the block.  I don’t have an fsync to input to it nor do I have a use for the fsync output. So what do I do?

 

In my 1080P@60Hz 4 pixels per clock test the input clock ( HDMI RX 37.125 MHz I think) will be the same as the 1080P output clock (HDMI TX) which will both be much slower than the AXI clock (150 MHz).  Currently my Video In to AXI Stream output is enabling valid once every 4 clock cycles. Is there a reason why it’s not contiguous?  The FIFO is 2048 in the Video In to AXI Stream and only 1024 in the AXI Stream to Video Out.  For the heck of it I am bumping them both to 4096 for now.  I am getting an underflow on the AXI Stream to Video Out.  Is this because of the FIFOs or because I don’t have detection and synchronization?

 

I have attached screen shots of each of my IP customization pages (does not include change to 4096 FIFO size change) since I have not tested it.

 

Kerry

 

AXItoVideoOut.PNG
VideoIntoAXI.PNG
vtc_generation.PNG
vtc_constant.PNG
vtc_position.PNG
scaler_block_design.PNG
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1 Solution

Accepted Solutions
Moderator
Moderator
833 Views
Registered: ‎11-09-2015

Re: VPSS Scaler Only with Native Video Input and Output

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HI @kmwilliams,

 

Let me try to summarize what you are asking.

 

1. You are asking if a video pipe, ex the design from xapp1285, can work without a frame buffer.

If your clock for the AXI4S is fast enough (usually faster than the video clock) you will not need a frame buffer. However, I always see the frame buffer as a safety net in case your AXI4S clock is close from the video clock. It allow the IPs in the pipe to be able to use the blanking time to do their processing. On the forums, you can find a lot of cases where a member tried to remove the VDMA/frame buffer and it was causing issues. So I would recommend it, or at least a big fifo somewhere in the pipe.

 

2. Then you are asking if you should configure the AXI4-Stream to Video out in slave or master mode?

When the pipe does not contain a VDMA or Video frame buffer, it is recommended to use the slave mode to minimize the back-pressure to upstream masters.

 

3. Then you are asking if you should enable detection in the VTC

You already can get the resolution from the HDMI IP, thus there is no need to detect it again. Thus, no you do not need to enable detection

 

4. Finally you are asking why the tvalid is not contiguous and why you are getting underflow

This is typically why you should use a VDMA or frame buffer. The VPSS will introduce some latency and might make the tvalid not be contiguous and then you will not get enough data at the output.

You might want to increase the AXI4S frequency. You can also change the scaler option to bicubic or bilinear, this might help but you will loose in quality

 

Hopefully I answered all your questions,

 

Let me know if there is anything I missed.

 

Best Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
4 Replies
Contributor
Contributor
868 Views
Registered: ‎05-11-2018

Re: VPSS Scaler Only with Native Video Input and Output

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I also uploaded an example of how I am hooking up all 4 IP blocks.

 

Attaching the VPSS screenshots to this reply.

 

Kerry

VPSS_toplevel.PNG
VPSS_scaler.PNG
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Moderator
Moderator
834 Views
Registered: ‎11-09-2015

Re: VPSS Scaler Only with Native Video Input and Output

Jump to solution

HI @kmwilliams,

 

Let me try to summarize what you are asking.

 

1. You are asking if a video pipe, ex the design from xapp1285, can work without a frame buffer.

If your clock for the AXI4S is fast enough (usually faster than the video clock) you will not need a frame buffer. However, I always see the frame buffer as a safety net in case your AXI4S clock is close from the video clock. It allow the IPs in the pipe to be able to use the blanking time to do their processing. On the forums, you can find a lot of cases where a member tried to remove the VDMA/frame buffer and it was causing issues. So I would recommend it, or at least a big fifo somewhere in the pipe.

 

2. Then you are asking if you should configure the AXI4-Stream to Video out in slave or master mode?

When the pipe does not contain a VDMA or Video frame buffer, it is recommended to use the slave mode to minimize the back-pressure to upstream masters.

 

3. Then you are asking if you should enable detection in the VTC

You already can get the resolution from the HDMI IP, thus there is no need to detect it again. Thus, no you do not need to enable detection

 

4. Finally you are asking why the tvalid is not contiguous and why you are getting underflow

This is typically why you should use a VDMA or frame buffer. The VPSS will introduce some latency and might make the tvalid not be contiguous and then you will not get enough data at the output.

You might want to increase the AXI4S frequency. You can also change the scaler option to bicubic or bilinear, this might help but you will loose in quality

 

Hopefully I answered all your questions,

 

Let me know if there is anything I missed.

 

Best Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Highlighted
Moderator
Moderator
792 Views
Registered: ‎11-09-2015

Re: VPSS Scaler Only with Native Video Input and Output

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HI @kmwilliams,

Was my reply enough for you on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
772 Views
Registered: ‎05-11-2018

Re: VPSS Scaler Only with Native Video Input and Output

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For now yes.  I was able to get the two Video to AXI and AXI to Video blocks working together.  Main issue was my source video was not what I thought it was.  Working on getting the scaler working.  Need to get the drivers operational as per my other thread you just responded too.

Thank you

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