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Explorer
Explorer
387 Views
Registered: ‎10-24-2008

VPSS Video Processing Subsystem - deploying the VPSS scaler in an time-division multiplexed fashion

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Please consider a use case example in which we have eight or sixteen 1080p30 video streams that we wish to scale down to CIF resolution (thus requiring deinterlacing).  These sixteen video streams are ingress to the FPGA via four MIPI interfaces and will be passed to the VCU for encoding.  How can we ascertain the minimum number of VPSS scaler IPs required for this application?  We would like to TDM the VPSS scaler IP in order to use the fewest possible number of instances of the VPSS IP.

Any insights that you can provide as to how such a use case can be implemented as well as the minimum number of instances required would be greatly appreciated.  Our target is a ZU7EV device.

--Quenton

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Explorer
Explorer
320 Views
Registered: ‎10-24-2008

Re: VPSS Video Processing Subsystem - deploying the VPSS scaler in an time-division multiplexed fashion

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Thanks Florent!  @florentw

We will indeed investigate this.  I have just cc'd you on an email trail offline.  I very much appreciate your feedback on this.

--Quenton

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Moderator
Moderator
338 Views
Registered: ‎11-09-2015

Re: VPSS Video Processing Subsystem - deploying the VPSS scaler in an time-division multiplexed fashion

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Hi Quenton @qhall,

You might want to look at the multi-scalar IP and the pg325. Of course you will still require one deinterlacer for each stream.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
321 Views
Registered: ‎10-24-2008

Re: VPSS Video Processing Subsystem - deploying the VPSS scaler in an time-division multiplexed fashion

Jump to solution

Thanks Florent!  @florentw

We will indeed investigate this.  I have just cc'd you on an email trail offline.  I very much appreciate your feedback on this.

--Quenton

0 Kudos