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Contributor
Contributor
1,355 Views
Registered: ‎05-02-2018

VPSS ip Timing Violation

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Hi,

 

  There are many timing violations when I using Video Processing Subsystem (v2.0),Xilinx's ip is a blackbox which I cannot change it's code.So,how can I eliminate the timing violation?

 

Violation path:  MIG-->MMCM-->VPSS

2.png

4.png

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Scholar watari
Scholar
1,270 Views
Registered: ‎06-16-2013

Re: VPSS ip Timing Violation

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Hi @gandics

 

> 1) I want to isolate data and clock between each module,by using FIFO and MMCM,to avoid timing violation.Are there any other solutions?

 

Would you use "set_false_path" setting to ignore clock domain crossing, if possible ?

I guess, almost all timing violation are ignorble.

But I can not confirm them without timing report.

 

> 2) Bandwidth might not enough if I change the Pixel Per Clock configuration.Are there any other solutions?

 

What do you mean "Bandwidth" ? Do you use external DRAM as frame buffer ?

If there is DRAM as frame buffer, you should change dram clock frequency.

If there is not DRAM, you should change line buffer size.

 

Best regards,

 

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Moderator
Moderator
1,335 Views
Registered: ‎11-09-2015

Re: VPSS ip Timing Violation

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Hi @gandics,

 

By using a slower clock .

 

You might want to change you Pixel Per Clock configuration


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎10-04-2017

Re: VPSS ip Timing Violation

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Hi @gandics,

 

In addition to @florentw's suggestion, it may also help you to take a look at the VPSS's example designs. These are detailed in chapter 5 of PG231

 

2018-09-24 09_19_48-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

 

-Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Contributor
Contributor
1,293 Views
Registered: ‎05-02-2018

Re: VPSS ip Timing Violation

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Hi @florentw,

 

Thanks for your advise!

 

I am using xc7a200tfbg676-2 device with 4 channel 1080p(1920x1080 148.5MHz) inputs.

 

According to the datasheet,VPSS  Maximum Frequencies Artix® -7 devices with –2 speed grade or higher is 150 MHz.

 

Input delay and clock constrains added,timing is ok,when I connect 4 channel input to the same ports. However,timing violation appearance when I connect to the individual input ports.

 

Dataflow and Utilization below.

VIP:

     ( vid2axi4s -> vpss ) x4 -> mix -> axi4s2vid

jiagou.png

 

Utilization.png

 

 

Here is my questions:

1) I want to isolate data and clock between each module,by using FIFO and MMCM,to avoid timing violation.Are there any other solutions?

 

2) Bandwidth might not enough if I change the Pixel Per Clock configuration.Are there any other solutions?

 

 

Thanks!

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Contributor
Contributor
1,292 Views
Registered: ‎05-02-2018

Re: VPSS ip Timing Violation

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Hi @samk

 

Thanks for your advise!

 

I am using xc7a200tfbg676-2 device with 4 channel 1080p(1920x1080 148.5MHz) inputs.

 

According to the datasheet,VPSS  Maximum Frequencies Artix® -7 devices with –2 speed grade or higher is 150 MHz.

 

Input delay and clock constrains added,timing is ok,when I connect 4 channel input to the same ports. However,timing violation appearance when I connect to the individual input ports.

 

Dataflow and Utilization below.

VIP:

     ( vid2axi4s -> vpss ) x4 -> mix -> axi4s2vid

jiagou.png

 

Utilization.png

 

 

Here is my questions:

1) I want to isolate data and clock between each module,by using FIFO and MMCM,to avoid timing violation.Are there any other solutions?

 

2) Bandwidth might not enough if I change the Pixel Per Clock configuration.Are there any other solutions?

 

 

Thanks!

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Scholar watari
Scholar
1,271 Views
Registered: ‎06-16-2013

Re: VPSS ip Timing Violation

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Hi @gandics

 

> 1) I want to isolate data and clock between each module,by using FIFO and MMCM,to avoid timing violation.Are there any other solutions?

 

Would you use "set_false_path" setting to ignore clock domain crossing, if possible ?

I guess, almost all timing violation are ignorble.

But I can not confirm them without timing report.

 

> 2) Bandwidth might not enough if I change the Pixel Per Clock configuration.Are there any other solutions?

 

What do you mean "Bandwidth" ? Do you use external DRAM as frame buffer ?

If there is DRAM as frame buffer, you should change dram clock frequency.

If there is not DRAM, you should change line buffer size.

 

Best regards,

 

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Contributor
Contributor
1,246 Views
Registered: ‎05-02-2018

Re: VPSS ip Timing Violation

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Hi @watari

 

Thanks for your reply!
 
1)Following your suggestion,I check the timing report(appendix:Timing_report.xls)
 
There are thousands of violations for the VPSS Intra-Clock path,which in the same clock domain,no clock domain crossing.
Almost all of the violations are the RST signal(for the FDRE,DSP48E,...)
 
I will reset&reconfigure VPSS mode in run-time for the resolution changing,so i think these RST signal violations might need to be removed.
 
2)Yes,I use 2 external DDR3-SDRAM as frame buffer for VPSS.
 
For 4 channel VPSS dataflow,1920*1080p @ 60fps,RGB(24bit),m_axi_mm bus(wr&rd)
Bandwith required: 4 * 1920columns * 1080rows * 60fps * 24bit * 2 = 2985 MByte/s
 
For 2* DDR3-SDRAM
Bandwith provided: 800Mhz * (16+16)bit = 3200 MByte/s
 
If sample per clock is 2
Bandwith required: 2985 * 2 >  3200 MByte/s
 
I am not sure whether calculated correctly or not ^_^
 
MIG configuration file below:
 
<MemoryDevice>DDR3_SDRAM/Components/MT41J128M16XX125</MemoryDevice>                                                                                                                                                                                                                                                                             
<TimePeriod>2500</TimePeriod>                                                                                                                                                                                                                                                                                                                                            
<VccAuxIO>1.8V</VccAuxIO>                                                                                                                                                                                                                                                                                                                                                
<PHYRatio>4:1</PHYRatio>                                                                                                                                                                                                                                                                                                                                                 
<InputClkFreq>200</InputClkFreq>                                                                                                                                                                                                                                                                                                                                         
<UIExtraClocks>0</UIExtraClocks>                                                                                                                                                                                                                                                                                                                                         
<MMCM_VCO>800</MMCM_VCO>
        <MMCMClkOut0>1.000</MMCMClkOut0>                                                                                                                                                                                                                                                                                                                                        
<MMCMClkOut1>1</MMCMClkOut1>                                                                                                                                                                                                                                                                                                                                             
<MMCMClkOut2>1</MMCMClkOut2>                                                                                                                                                                                                                                                                                                                                             
<MMCMClkOut3>1</MMCMClkOut3>                                                                                                                                                                                                                                                                                                                                             
<MMCMClkOut4>1</MMCMClkOut4>                                                                                                                                                                                                                                                                                                                                             
<DataWidth>32</DataWidth>                                                                                                                                                                                                                                                                                                                                                
<DeepMemory>1</DeepMemory>                                                                                                                                                                                                                                                                                                                                               
<DataMask>1</DataMask>                                                                                                                                                                                                                                                                                                                                                        <ECC>Disabled</ECC>                                                                                                                                                                                                                                                                                                                                                      
<Ordering>Normal</Ordering>                                                                                                                                                                  <BankMachineCnt>4</BankMachineCnt>                                                                                                                                                                                                                                                                                                                                       
<CustomPart>FALSE</CustomPart>                                                                                                                                                                                                                                                                                                                                              <NewPartName></NewPartName>                                                                                                                                                                                                                                                                                                                                              
<RowAddress>14</RowAddress>                                                                                                                                                                                                                                                                                                                                                   <ColAddress>10</ColAddress>                                                                                                                                                                                                                                                                                                                                              
<BankAddress>3</BankAddress>                                                                                                                                                                                                                                                                                                                                                     <MemoryVoltage>1.5V</MemoryVoltage>                                                                                                                                                                                                                                                                                                                                      
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
 
Thanks!  
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Contributor
Contributor
1,234 Views
Registered: ‎05-02-2018

Re: VPSS ip Timing Violation

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Hi @florentw

 

Oh~I understand what your mean!

 

Using 2  Pixel Per Clock will not enlarge the bandwith require,bandwith depend on input resolution and frame rate.

 

I will use slower clock for microblaze axi control clock and stream data axis clock.

 

Thanks!

 

 

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Contributor
Contributor
1,230 Views
Registered: ‎05-02-2018

Re: VPSS ip Timing Violation

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Hi @watari

 

After replying your post,I calculate and consider again.

 

Using 2  Pixel Per Clock will not enlarge the bandwith require,bandwith depend on input resolution and frame rate.

 

I will use slower clock for microblaze axi control clock and stream data axis clock.

 

Thanks!

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Moderator
Moderator
1,178 Views
Registered: ‎11-09-2015

Re: VPSS ip Timing Violation

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HI @gandics,

 

Do you have any updates on this?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
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Registered: ‎05-02-2018

Re: VPSS ip Timing Violation

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Thank you!:)
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