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Contributor
Contributor
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Registered: ‎12-27-2018

VPSS resources

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Dear Forum

I am using VPSS with Zynq UltraSCale device (9EG speed grade:2).

Do you have any suggestion to lower resource usage for VPSS (fully fledge setting) ?

I am targeting around 20K LUT or 22K LUT at max (for YUV422 8 bit/10 bit only. RGB 8bit, RAW10)

Currently it is around 33.5K LUT with 93 block BRAM.

Best regards.

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Moderator
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Registered: ‎11-09-2015

Re: VPSS resources

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HI @yuko.2828 

If you are not using all the sub-module of the VPSS maybe you should use the sub-modules individually (ex. scaler only..).

Also you can change the algorithm of the scaler or deinterlacer to reduce resources usage.

As mentioned by @watari , reducing the ppc will reduce the resources.

Finally, make sure you are supporting only the color format you need


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Contributor
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Registered: ‎12-27-2018

Re: VPSS resources

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Have been experimenting using Vivado synthesis strategy in these few days.

Nothing really help.....

image001.png
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Mentor
Mentor
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Registered: ‎06-16-2013

Re: VPSS resources

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Hi @yuko.2828 

 

Do you recognize which module dose it consume in the most ?

Also, how much timing mergine does your deigns have in VPSS ?

 

Best regards,

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Contributor
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Registered: ‎12-27-2018

Re: VPSS resources

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@watari Thank you !!

I think Vivado do a good job synthesis VPSS IP, but this IP is just too big, also me too lazy to create new module from zero for my design.

 

Answering your question.

 

1.  slack:1.38ns

Worst Path :

***/v_proc_ss_0/inst/hcr/inst/v_hcresampler_CTRL_s_axi_U/int_HwReg_coefs_1_0_reg[15]/C

***/v_proc_ss_0/inst/hcr/inst/v_hcresampler_core_U0/select_ln385_4_reg_2114_reg[0]/CE

My FPGA only has 2 VPSS modules.

 

2. VPSS is the biggest one. For one single module : 33.5K LUT with 93 block BRAM. I seems not so big.

   But if you want to implement 4 module, so 33.5K LUT x4 = 134k is too big.

 

Do you have any idea to cut the LUT resource ?

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Mentor
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Registered: ‎06-16-2013

Re: VPSS resources

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Hi @yuko.2828 

 

It seems you try to implement VPSS for 4K resolution..

If my understanding is correct, I recommend to consider 2 pixel per clock mode instead of 4 pixel per clock mode.

 

Also, it seems your design spends more line memories.

If my understanding is correct, I suggest you to optimize your video path (consider proper buffer size), too.

 

Best regards,

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Moderator
Moderator
235 Views
Registered: ‎11-09-2015

Re: VPSS resources

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HI @yuko.2828 

If you are not using all the sub-module of the VPSS maybe you should use the sub-modules individually (ex. scaler only..).

Also you can change the algorithm of the scaler or deinterlacer to reduce resources usage.

As mentioned by @watari , reducing the ppc will reduce the resources.

Finally, make sure you are supporting only the color format you need


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Contributor
Contributor
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Registered: ‎12-27-2018

Re: VPSS resources

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Thank you for your great help and advice.
I am implementing 4-channel with VPSS and HDMI, my design is already using 2 pixel per clock configuration !!  Optimizing my own logic now, since VPSS does not much help.

Now, I am thinking to use only Scaler, since this is mandatory function. 
 
Best regards.
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Contributor
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Registered: ‎12-27-2018

Re: VPSS resources

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@watari, @florentw

Okay great, using scalar only and I can implement my design successfully.

Thank you !

 

@florentw

I am expecting that Xilinx should must have a hiden option, to remove or to keep unnecessary logic.

Having Deinterlacer will be better tough (^-^)

 

Thank you.

Best regards

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Moderator
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Registered: ‎11-09-2015

Re: VPSS resources

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Hi @yuko.2828 

No there is no magic switch. If there is unnecessary logic, it will be removed during synthesis.

If the development team had find better version in term of resources, then it would be the default version of the IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**