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Observer
Observer
5,600 Views
Registered: ‎08-14-2014

VVD 2016.2 DisplayPort driver bug report

Hello,

 

I found a bug in DisplayPort driver v5.0 with vivado 2016.2.

 

xdp_selftest.c table "TxResetValues" defined XDP_TX_PHY_CONFIG default value as 0x03. While I tried to read this register, it should be 0x200003. Refer to PG064 table 2-9, it should also be 0x200003.

 

So is the example release without testing?

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Xilinx Employee
Xilinx Employee
5,580 Views
Registered: ‎07-31-2012

Re: VVD 2016.2 DisplayPort driver bug report

 

Do you mean that you are reading a value of 0x200003 when it is expected to be 0x03?

 

The PG sure mentions that this should be 0x03 and the driver too mentions this correctly as 0x03.

Thanks,
Anirudh

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Observer
Observer
5,576 Views
Registered: ‎08-14-2014

Re: VVD 2016.2 DisplayPort driver bug report

PG064 page31 described the bit 21 of reg 0x200 as below:

 

[21] – Set to 1 to enable the 8B10B coding. Default is 1. SW should not unset this bit for normal operation of TX PHY.

 

So I considered that bit 21 should be 1 by default.

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Xilinx Employee
Xilinx Employee
5,564 Views
Registered: ‎07-31-2012

Re: VVD 2016.2 DisplayPort driver bug report

@wangxiguang,

 

As mentioned in the PG this bit should not be change during normal operation. However during reset (which is not normal operation) it is fine to reset this as we do not care about 8b/10b during reset.

Thanks,
Anirudh

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Observer
Observer
5,557 Views
Registered: ‎08-14-2014

Re: VVD 2016.2 DisplayPort driver bug report

So how can explain that I read 0x200003 from reg 0x200?

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Xilinx Employee
Xilinx Employee
5,552 Views
Registered: ‎07-31-2012

Re: VVD 2016.2 DisplayPort driver bug report

Ok, so it wasn't clear from the question if the value 0x200003 was what you read or what you wanted to write.

Does the self_test throw an error about the mismatch?
Thanks,
Anirudh

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Observer
Observer
5,536 Views
Registered: ‎08-14-2014

Re: VVD 2016.2 DisplayPort driver bug report

Yes. The self_test throw an error.

 

The self_test read reg 0x200 and got 0x200003. Other regs are all correct.

 

So I checked the PG064 and found the reg may be 0x200003 instead of 0x03, if bit 21 is '1' by default.

 

I think it may be a bug of self_test example.

 

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Xilinx Employee
Xilinx Employee
5,498 Views
Registered: ‎07-31-2012

Re: VVD 2016.2 DisplayPort driver bug report

Thanks for pointing this out. I have reported this internally through a Change request.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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