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Video Beginner Series 1: Introduction to Digital Video

Introduction

 

This Video Beginner Series 1 introduces the basics of digital imaging and video. The tutorial will help you understand how to work with video signals with Vivado and Xilinx All Programmable devices.

 

 

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Summary

 

1. What is an image?

2. Introduction to Video

3. Tutorial - Working with native video in Vivado

4. What Next?

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Video Beginner Series 1: Introduction to Digital Video - What is an image?

What is an image?

 

An image is an array of pixels (the word pixel comes from picture (x) elements).

 

For a Black and white image, a pixel is defined by one value representing the brightness. If this value is high, the pixel will be bright (white) and if it is low, the pixel will be dark (black).

 

For a colour image, in most cases the pixel is composed of three values: its level of Red, its level of Green and its level of Blue (this is why we usually call colour images RGB images (for Red Green and Blue)). The combination of these 3 values will give the final colour of the pixel.

 

For example, in a lot a software tools, you can create customs colours by setting the value of Red, Green and Blue. As shown in the figure below, if you select the maximum value for Green and Red (255 in this case) and 0 for Blue, you obtain the colour Yellow.

1.jpg

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Video Beginner Series 1: Introduction to Digital Video - Introduction to Video

Introduction to Video

 

A video is a series of images changing at a particular frequency (typically 50 or 60 times per second).

 

When transmitted from a source to a monitor, a video is sent one image at the time. Each image is sent line by line starting with the top line and each line is sent pixel by pixel starting with the left pixel.

 

For example, the figure below shows how a 3x3 pixel image could be sent to a monitor using 3 data lanes (Red Green Blue).

 

2.png

 

Along with the pixel values, timing information (carried by the timing signals) is sent to describe the video frame timing. A video frame (one single image of a video) comprises active video and blanking periods.

 

The timing signals are horizontal and vertical blanking which represent the blanking period (commonly called hblank and vblank) and the horizontal and vertical synchronisation (commonly called hsync and vsync) which happen during the blanking period and are used to indicate when a new line (hsync) or a new frame (vsync) is starting.

 

Good to know: The time between the start of a blanking period and the start of a synchronization signal is called front porch while the time between the end of a synchronisation signal and the end of a blanking signal is called the back porch.

 

The figure below shows an example of a video frame along with the synchronization signals.

 

3.png

 

Video systems may utilize different combinations of blanking, synchronization or active signals with various polarities. For example, a VGA interface is only using hsync and vsync.

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Video Beginner Series 1: Introduction to Digital Video - Tutorial - Working with native video in Vivado

Tutorial - Working with native video in Vivado

 

Note: This tutorial is intended to be used only with 2018.1

 

Build the Vivado project

 

  1. Download the tutorial files and unzip the folder

  2. Open Vivado 2018.1

  3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0001)

  4. In the tcl console, source the script tcl (source ./create_proj.tcl)

 

Understand the design

 

5. In Vivado, in the source window, double click on the block design (vga_source_i) to open it

 4.png

 

 6. You can then view the diagram of the design

 5.png

 

7. The VGA_SOURCE IP is an IP which generate VGA signals at 1280x1024@60Hz resolution (the width of the video is 1280, the height is 1024 and the image is updated every 16.66ms (1/60Hz)). For this resolution, it needs a video clock with a frequency of 108MHz. clk_in is a 100MHz clock. The Clocking Wizard IP is used to generate the 108MHz clock from the 100MHz input clock.

 

8.(Optional) - Test the design on board (for Zedboard users)

  1. Zedboard users can generate a bitstream and run it on the Zedboard. With a VGA monitor connected (supporting 1280x1024), you can see a pattern on the monitor

6.jpg

 

 

Understand the timing signals

 

9. Launch the simulation for the design (Run Simulation > Run Behavioral Simulation)

10. Run the simulation for 50ms. When clicking on the icon sim.JPG, the simulation will run for the time set in the field next to it.


7.png

 

11. Set the cursor on the second rising edge of active_video_out. It shows the simulation time 16.763147us

8.png

 

12. Click on the Next Transition button to move the cursor to the next falling edge

9.png


      Q1. What is the time for this falling edge?
      Q2. What does the high time of active_video_out represent?
      Q3. In terms of a Video data line, what does the signal hsync indicate?

 

13. Click on the first rising edge of vsync at time 16.01772ms

 10.png

 

 14. Click two times on the Next Transition button to move the cursor to the next rising edge
      Q4. What is the simulation time for this rising edge?
      Q5. What does the time between two vsync pulses represent?
      Q6. What does the signal vsync indicate?

 

15. Close the simulation and close Vivado

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Video Beginner Series 1: Introduction to Digital Video - What next?

What Next?

 

 

 

  • You liked this Video Series?
    • You can give Kudos using the Kudos button  kudos.PNG
    • Make sure you are following the Xilinx Video Series topic to be informed when an new topic is published (Go to the Xilinx Video Series topic > Options > Subscribe)
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Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**