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Video Beginner Series 12: Using the AXI4-Stream Infrastructure IP Suite (Part 1)

Introduction

The AXI4-Stream Infrastructure IP Suite is a collection of modular IP cores that can be used to rapidly connect AXI4-Stream master/slave IP systems in an efficient manner.

 

All the IPs included in the AXI4-Stream Infrastructure IP Suite are documented in the PG085.

 

This Video Beginner Series 12 shows how to use the some AXI4-Stream infrastructure IP Suite to connect AXI4-Stream interfaces together when building a video system

 

1.png

 

 

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Summary

 

1. Tutorial – Using the AXI4-Stream Infrastructure IP Suite (1)

2. What next?

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Video Beginner Series 12 - Tutorial – Using the AXI4-Stream Infrastructure IP Suite (1)

Tutorial – Using the AXI4-Stream Infrastructure IP Suite (1)

 

Note 1: This tutorial is intended to be used only with Vivado 2018.1 and only in simulation

Note 2: A valid license for the Test Pattern Generator is required to build the design.

 

Build the Vivado project

 

  1. Download the tutorial files and unzip the folder

  2. Open Vivado 2018.1

  3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0012)

  4. In the tcl console, source the script tcl (source ./create_proj.tcl)

Different data width between interfaces (padded data)

 

The design is built to output RGB video data. We will now try to output YCbCr422. The TPG output format can be dynamically between YUV420, YUV422, YUV444 and RGB, thus its configuration does not need to be changed. We only need to change the configuration of the AXI4-Stream to video Out IP.

 

  1. Double click on the AXI4-Stream to video Out IP to open its configuration GUI.

  2. Change the Video Format settings to Manual and change its value to YUV4:2:2: and click OK
    2.png
  1. If we validate the block design we get the following critical warning from Vivado

 

[BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /v_axi4s_vid_out_0/video_in(2) and 
/v_tpg_0/m_axis_video(3)

 

 

The reason for this critical warning is because the width of tdata does not match between the TPG IP output (24 bits or 3 bytes) and the AXI4-Stream to Video Out IP output (16 bits or 2 bytes) as we can see if we expand the interfaces in the Block Design.

 3.png

 

 

The tdata width of the TPG IP is 24 bits because the TPG IP can output different video format. In case of RGB or YUV444, with 8 pixels per component, the width of one pixel is 24 bits.

 

However, we know that this data bus will only output YUV422 as we will configure the TPG to output YUV422 data. This means that the bits [23:16] of tdata will be padding bits and will not contain the video information.

 

The IP to connect the 2 interfaces in this case is the AXI4-Stream Subset Converter IP

 

  1. Add an AXI4-Stream Subset Converter IP and connect it between the TPG and the AXI4-Stream to Video IPs.
    4.png
  1. Double click on the AXI4-Stream Subset Converter IP to configure it. Change the TDATA Width configuration to Manual for both the Slave and the Master interface. Change the value to 3 for the Slave and 2 for the Master and click OK
    5.png

 

  1. Validate the block design. You should get no errors or critical warnings
    6.png

 

Different ppc configuration between interfaces

Note this would work only if the image width is dividable by the number of pixels per clock.

In some cases, you might have a different Pixel Per Clock (PPC) configuration between the AXI4-Stream master and slave. For example, we will configure the Test Pattern Generator IP to output 2 pixels per clocks while the AXI4-Stream to Video Out IP will only accept 1 PPC data. It is important to note how the data are sent over the AXI4-Stream interface when sending multiple pixels per clock. As per the UG934, which defines the AXI4-Stream interface between Xilinx Video IPs, the “pixels should be packed from least significant bit (LSB) to MSB, e.g., the least significant pixel should correspond to the left-most pixel in a scanline, or to the pixel captured earliest in time”. This means that the padding bits will be on the MSB of the full data (i.e. not at the MSB of each pixel).

 

7.PNG

 

  1. Double click on the TPG IP to open its configuration GUI

  2. Change the Samples per Clock value to 2 and click OK
    8.png

 

  1. Validate the block design. You should get a critical warning because the tdata width of the TPG output is now 6 bytes (48 bits)

 

[BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /axis_subset_converter_0/S_AXIS(3) and 
/v_tpg_0/m_axis_video(6)

 

 

  1. The first step is to get rid of the padding bits using the AXI4-Stream Subset Converter IP we already have in our design. To keep only the useful information, we need to set the slave tdata width to 6 bytes and the master tdata width to 4 bytes (2 pixels of 2 bytes). Because of the way the AXI4-Stream Data Width converter IP is done we also need to increase the width of tuser to 4 bits (with the actual tuser value mapped to the bit 0).
    9.png

 

Then we need to send the pixels individually for each clock cycle (i.e. 1 ppc). To do this we can use the AXI4-Stream Data Width converter IP.

  1. Add a AXI4-Stream Data Width converter IP to the block design and connect it between the AXI4-Stream Subset Converter IP and the AXI4-Stream to Video Out IP.
    10.png

 

  1. Double click on the to open its configuration GUI and make sure the Master tdata width is 2 bytes and change the value for TUSER bits per byte to 1
    11.png

 

  1. Validate the design. You should have no errors or critical warnings.

This design should work. However, if we check the width of tuser of the AXI4-Stream Data Width converter IP output (2 bits) and the AXI4-Stream to Video Out IP input (1 bit) they do not match.

  1. To correct this, we can place another AXI4-Stream Subset Converter IP between these 2 IPs
    13.png

 

  1. And we need to configure the master interface tuser width to 1 and make sure it is mapped to the lower bit of the input
    14.png

 

  1. Validate the block design. You should have no errors or critical warnings.

 

Interfaces with different clocks

As the TPG IP is sending 2 PPC and the AXI4-Stream to Video Out IP only accepts 1 PPC, we could reduce the frequency of the TPG IP.

  1. Source the script src/tcl/change_clock_TPG.tcl from the tcl command

  2. Validate the design. You should get the following errors:

 

[BD 41-237] Bus Interface property FREQ_HZ does not match between /axis_subset_converter_0/S_AXIS(40000000) and 
/v_tpg_0/m_axis_video(20000000) [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /axis_subset_converter_0/S_AXIS(AXI4S_bd_aclk_40MHz) and
/v_tpg_0/m_axis_video(AXI4S_bd_aclk_20MHz)

 

 

  1. To solve these errors, add an AXI4-Stream Clock Converter IP between the TPG IP and the first AXI4-Stream Subset Converter IP
    15.png

 

  1. Validate the block design, you should get no errors or critical warnings

  2. Close Vivado

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Video Beginner Series 12 - What Next?

What Next?

 

 

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Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**