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Registered: ‎11-09-2015

Video Beginner Series 13: Using the AXI4-Stream Infrastructure IP Suite (Part 2)

Introduction

 

The AXI4-Stream Infrastructure IP Suite is a collection of modular IP cores that can be used to rapidly connect AXI4-Stream master/slave IP systems in an efficient manner.

 

All the IPs included in the AXI4-Stream Infrastructure IP Suite are documented in the PG085.

 

This Video Beginner Series 13 is a continuation of the Video Beginner 12 on how to use the some AXI4-Stream infrastructure IP Suite to connect AXI4-Stream interfaces together when building a video system

 

1.png

 

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Summary

 

1. Tutorial – Using the AXI4-Stream Infrastructure IP Suite (2)

2. What next?

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
2 Replies
Moderator
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Registered: ‎11-09-2015

Video Beginner Series 13 - Tutorial – Using the AXI4-Stream Infrastructure IP Suite (2)

Tutorial – Using the AXI4-Stream Infrastructure IP Suite (2)

 

Note 1: This tutorial is intended to be used only with Vivado 2018.1 and only in simulation

Note 2: A valid license for the Test Pattern Generator is required to build the design.

 

Build the Vivado project

 

  1. Download the tutorial files and unzip the folder

  2. Open Vivado 2018.1

  3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0013)

  4. In the tcl console, source the script tcl (source ./create_proj.tcl)

In this design, the Test Pattern Generator IP is expected to output RGB data.

Sending the same data to multiple slaves

In some cases, it can be useful to send the same data to multiple slaves (for example to get the same video on multiple monitors). For that purpose, we can use the AXI4-Stream broadcaster.

In our case we will use this IP to split the color components (Red, Green and Blue) on 3 different interfaces, to do, for example, different processing on each color.

  1. Add an AXI4-Stream Broadcaster IP and connect it to the TPG IP output
    2.png

 

  1. Validate the BD design to get the parameters from the m_axis_video output from the TPG propagated to the S_AXIS input of the AXI4-Stream Broadcaster IP

  2. Double-click on the AXI4-Stream Broadcaster IP to open its configuration GUI.

  3. Change the following settings in the AXI4-Stream Broadcaster page
    • Number of Master Interfaces: 3
    • MI TDATA Width: Manual – 1 byte
      3.png

 

  1. Change the following settings in the Stream Splitting Options page
  • M00 TDATA Remap String: tdata[7:0]
  • M01 TDATA Remap String: tdata[15:8]
  • M02 TDATA Remap String: tdata[23:16]
    4.png

Combining streams

 

Before doing any processing on the colour components, we will try to reconstruct the RGB stream with the 3 components. For this we will use an AXI4-Stream Combiner IP.

 

  1. Add an AXI4-Stream Combiner IP to the design
  2. Double click on the AXI4-Stream Combiner IP to open its configuration GUI

  3. Change the following parameters:
    • Number of Slave Interfaces: 3
    • TDATA Width: Manual – 1 byte
    • Enable TLAST: Manual - Yes
    • TUSER Width: Manual – 1
    • TID Width: Manual – 0
    • TDEST Width: Manual - 0

      5.png

 

  1. Connect the AXI4-Stream Combiner IP to the AXI4-Stream Broadcaster IP
    6.png

The AXI4-Stream Combiner IP will concatenate the tuser signals from all the interface to output a 3-bit wide bus. However, for video data we should have only one bit for tuser. We can fix this using an AXI4-Stream Subset Converter IP

  1. Add an AXI4-Stream Subset Converter IP to the design and connect it to the AXI4-Stream converter.
    7.png

  2. Double-click on the AXI4-Stream Subset Converter IP to open its configuration GUI and change the TUSER WIDTH for the master interface to 1
    8.png

 

  1. Connect the AXI4-Stream output of the AXI4-Stream Subset Converter IP to the AXIS_out output port of the BD
    9.png
  2. We can verify with GIMP tool that the all video chain is working by running the simulation for 14ms. The output image (proj_1.sim/sim_1/behave/xsim/ ppm) is the expected pattern.
    10.png

 

Debugging Issues

One of the most common issue that can happen when using the AXI4-Stream Broadcaster or the AXI4-Stream Combiner IPs is due to the fact that all the streams are not consuming data at the same speed or do not have data ready at the same time. For example, we will try to add a dummy IP to do some processing only on the green component.

  1. Add the IP “Green_processing_v1.0” to the design. Note: this IP is a dummy IP (no real function) created only to be used for this Xilinx Video Beginner Series. It was added to the project using a local repository.

  2. Connect the Green Procession IP on the Green data path (M00 output of the AXI4-Stream Broadcaster IP to the S00 input of the AXI4-Stream Combiner IP).
    11.png

 

  1. Launch the simulation for 1ms. We can see that the TPG is ready to send data (TPG’s output TVALID is high) and the final output of the design is ready to accept data (tready input of the AXI4-Stream to Video Out is high) however no data are transmitted (tvalid output of the AXI4-Stream to Video Out is low).
    12.png

 

 

To investigate we can do step by step starting by one side of the processing chain. For example, we will start from the source side. We know that the TPG is ready to send data, but the AXI4-Stream Broadcaster IP is not ready to accept data (TREADY input of the TPG (output of the broadcaster) is low). We can investigate on the output interfaces of the broadcaster IP.

 

  1. Add the signals from the M_AXIS interface of AXI-Stream Broadcaster IP to the simulation:
    1. In the Scope window select the AXI4-Stream Broadcaster IP
    2. In the Objects window, select all the signals starting by m_axis (note: tid and tdest are not needed are not used for most video systems)
    3. Right-click on the selection and click Add to Wave Window
      13.png
  1. Restart the simulation and run it again for 1ms

  2. If we look at the TREADY signals input of the AXI4-Stream Broadcaster IP we can see that the tready signals are low for the red and blue colours path (m_axis_tready[2] and m_axis_tready[1]). Because these signals are low, the AXI4-Stream Braodcaster IP is not accepting data. However, we can see that the first pixel was transmitted on the green colour data path (m_axis_tvalid[0] and m_axis_tready[0] are both high at the same time)
    14.png

 

  1. m_axis_tready[2] and m_axis_tready[1] are connected directly to the AXI4-Stream Combiner IP. We can investigate by adding the signals from the S_AXIS interface of AXI-Stream Combiner IP to the simulation:
    1. In the Scope window select the AXI4-Stream Combiner IP
    2. In the Objects window, select all the signals starting by s_axis (note: tid and tdest are not needed are not used for most video systems)
    3. Right-click on the selection and click Add to Wave Window
  2. Restart the simulation and run it again for 1ms

  3. On the simulation we can see that the AXI4-Stream Combiner IP is not asserting the signals tready for all its interface inputs.
    15.png

 

The AXI4-Stream Combiner IP is not asserting the signals tready is because he is waiting on all the interfaces to assert tvalid which is not the case on the interface S00 corresponding to the green colour path. The reason for that is because the dummy Green_Processing IP I have created is waiting for several data words before outputting its first data. However, because it is not outputting any data the other colours paths are stuck.

 

We can solve this problem by adding an AXI4-Stream Data FIFO IP on the path for the Red and Blue colour paths

 

  1. Add an AXI4-Stream Data FIFO IP and connect it between the M01_AXIS output from the AXI4-Stream Broadcaster IP and the S01_AXIS input from the AXI4-Stream Combiner IP
    16.png

 

  1. Add another AXI4-Stream Data FIFO IP and connect it between the M01_AXIS output from the AXI4-Stream Broadcaster IP and the S01_AXIS input from the AXI4-Stream Combiner IP
    17.png
  1. Run the simulation for 14ms
  2. We can see that now the image is outputted
    18.png

 

  1. And we can check with GIMP that the output image is correctly generated

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Video Beginner Series 13 - What Next?

What Next?

 

 

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Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**