UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Moderator
Moderator
1,483 Views
Registered: ‎11-09-2015

Video Beginner Series 16: Understanding Video Timing with the VTC IP


Introduction

 

Video timing is the heart beat of a video system. Thus, its understanding is important for a good foundation to video system development. In this Video Beginner Series 16, we will use the Xilinx Video Timing Controller (VTC) IP configured as generator. This Video Beginner Series is intended to complete the Video Beginner Series 1 on the timing part.

 

1.png

 

For documentation on the Xilinx Video Timing Controller IP refer to its product guide PG016.


Summary

 

1. Understanding video timing parameters

2. Tutorial - Understanding Video Timing with the VTC IP

3. What Next?


Understanding video timing parameters

 

The table below is an example of timing parameters you can get for a specific resolution. In this case, it is the timing parameters for 640x480p @60 Hz.

2.JPG

 

To understand how this parameter are used, we can use an example: An image with 480 lines and 640 pixels per line. Each pixel will be name by its line and its column Pline,column. For example, the first pixel of the first line will be P1,1 and the last pixel of the first line P1,640.

 

3.png

 

Each active video line is enclosed by horizontal blanking periods during which horizontal sync signals will happen. The time between the beginning of the blanking period and the start of the sync is call front porch and the time between the end of the sync signals and the end of the blanking period is call back porch. The horizontal active time is the time between two horizontal blanking periods (excluding the time of the blanking period).

 

For example, this is how the second line would be transmitted:

4.png

 

Each frame is enclosed in vertical blanking periods during which vertical sync signals will happen. The vertical active time is the time between two vertical blanking periods.

5.png

 

In the name of the 640x480p @60Hz resolution you might have noticed two other elements in addition to the frame size:

  • The @60Hz: 640x480p @60Hz
  • The letter p: 640x480p @60Hz

The @60Hz can easily be found in the resolution table. This is the refresh rate. This means that there will be a new image at a 60Hz rate so 1 image per second. Note that in many case the refresh rate is not mentioned for 60Hz as it is a common case.

The letter p means that the video is sent as progressive or non-interlaced. Interlaced video sent only 1 line every 2 lines for each frame. We will see interlaced video in a future Video Series. In progressive mode, all the lines are sent to the monitor (or receiver).


 

Tutorial - Understanding Video Timing with the VTC IP

 

Note 1: This tutorial is intended to be used only with Vivado 2018.1

 

Build the Vivado project

 

  1. Download the tutorial files and unzip the folder

  2. Open Vivado 2018.1

  3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0016)

  4. In the tcl console, source the script tcl (source ./create_proj.tcl)

Check the configuration of the VTC

In the block design there is only the Video Timing Controller (VTC) connected. We can check how it is configured

  1. Double-click on the VTC to open its configuration GUI. On the “Detection/Generation” page we can see that only the generation part has been enabled.

    6.png
  1. Go to the “Default/Constant” page. The VTC has been configured with the default settings for 640x408p

    7.png

We can see that we can find some of the timing parameters for 640x480p from the previous table. Some other can be find by calculus:

 

  • Horizontal Settings
    • Active Size = Horizontal Active = 640 (pixels)
    • Frame Size = Horizontal Total = 800 (pixels)
    • Sync Start = Horizontal Active + Horizontal Front Porch = 656 (pixels)
    • Sync End = Sync Start + Horizontal sync = 752 (pixels)
  • Frame/Field 0 Vertical Settings
    • Active Size = Vertical Active = 480 (lines)
    • Frame size = Vertical Total = 525
    • Sync Start = 489 (lines)
      • This one is slightly different from the parameters (should be Vertical Active + Vertical Front Porch = 490). We will investigate this in simulation
    • Sync End = Sync Start + Vertical sync = 491

Note that there are no settings for the tome of the blanking signals. This is because the VTC will set them at the end of an active period and unset them at the beginning of the next active period.

 

  1. We can see that the Polarity of the Hsync and Vsync are not automatically set with the default mode. From the parameters we have, we can see that both should be low (negative) polarity. We can change these settings:
    8.png

 

  1. Click OK to apply the new parameters and to close the GUI.

  2. Save the Block Design and generate the BD output products

Check the values in simulation

  1. Launch the behavioral simulation and run it for 17 ms

  2. We can see that the Hsync and Vsync signals are active low as expected

  3. Find the first rising edge of active_video_out at 0.139us then click on the icon 15.png to go to the next falling edge. It is at 25.5598us. Thus, the time between both is 25.4208us. The period of the clock in this simulation is 39.72ns so the active_video_out signal was high for 640 period of the pixel clock (equivalent to 640 pixels). This is what we were expecting.

  4. Check the time between two falling edge of Hsync. We can see that it is 31.776us or 800 pixels as per the total horizontal size. This is the time of a line.

    9.png

 

  1. Check the time of the first rising edge of vblank_out (15.2462ms). This corresponds to 480 lines (31.776us * 480).

  2. Check the number of lines which happen between the start of Vblank and the start of Vsync

    10.png

 

We can see that the Vsync happens after 10 lines, which match the timing parameters for 640*480p@60Hz, but this is not what we were expecting from the VTC configuration. This is because there is one part of the configuration we haven’t looked at yet: The Horizontal Fine Adjustment.

Understand the Horizontal Fine Adjustment of the VTC IP

  1. Close the simulation and open the block design

  2. Open the configuration GUI of the VTC IP

  3. In the Default/Constant, we can see a section called “Frame/Field 0 Horizontal Fine Adjustment”

  4. Change the Video Mode from 640x480p to Custom to be able to change the settings (while having the 640x480p default for the other settings)

    11.png

 

  1. Change the Vsync Start value to 0 in fine adjustment

    12.png

  2. Save the Block Design

  3. Run the simulation for 17 ms

  4. Check the number of lines which happen between the start of Vblank and the start of Vsync

    13.png

We can see that the Vsync now happens after 9 lines (was 10 with the default configuration).

 

The Vertical parameters are usually defined in lines count. Thus, if you want to vary the time when vsync happens (same thing applies to the vblank) with a pixel clock precision, you will need use the Horizontal Fine Adjustment. The times start at the falling edge of hsync.

 

This small nuance can be spotted in the wording of PG016:

14.png

 

These settings can be useful when a receiver is requiring specific timing parameters.


 

What Next?

 

  • Do you have issues/questions following this Vivado Beginner Series?
    1. Search on the Xilinx forums for similar questions
    2. Create a new topic on the Video Board for your issue/question with the title starting with [Video Beginner Series 16] and followed by a quick description of your issue/question

 

  • You liked this Video Series?
    • You can give Kudos using the Kudos button  kudos.PNG
    • Make sure you are following the Xilinx Video Series topic to be informed when an new topic is published (Go to the Xilinx Video Series topic > Options > Subscribe)

subscribe.PNG

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**