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Registered: ‎11-09-2015

Video Beginner Series 18: Create a Video Crop IP using HLS (part 2)


Introduction

 

This Video Beginner Series 18 is a continuation of the Video Beginner Series 17. In this series we will test the Video Crop IP generated with Vivado HLS in RTL simulation with Vivado. We will use the test pattern generator as input stimuli and we will write the output to an image file.

1.png

 


Summary

 

1. Tutorial – Validating the video crop IP in RLT simulation

2. What Next?

 


 

Tutorial – Validating the video crop IP in RLT simulation

 

Note: This tutorial is intended to be used only with Vivado 2018.1

Build the Vivado project

  1. Download the tutorial files and unzip the folder

  2. Open Vivado 2018.1

  3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0018)

  4. In the tcl console, source the script tcl (source ./create_proj.tcl)

Note: A valid license for the Test Pattern Generator is required to build the design.

The design is based on the Xilinx Video Series 5.

Add the HLS IP to test to the design

  1. Right-click on the BD design and click on Add IP

  2. Search for crop and add the Video_crop IP

Note: The IP generated by HLS was extracted in the src/ip_repo directory and this directory has been added to the repository in Vivado. Refer to section Test the IP in Vivado Simulation of the Xilinx Video series 16 for information on these steps.

  1. If we double click on the video crop IP to open its configuration GUI, we can see that there is not parameter we can configure

 

2.png

 

  1. Connect the TPG’s AXI4 master interface to the Video_crop’s AXI4 slave interface.

  2. Connect the ap_clk, ap_reset_n, hsize_in and vsize in of the Video_crop IP to the BD’s inputs aclk_50MHz, areset_n_0, hsize and vsize.
  1. Expend the video_crop ap_ctrl interface and connect the pin ap_start to the BD’s input ap_start

 

  1. 3.png

     Expend the m_axis_video interface of the video crop and connect the pins TVALID, TREADY, TDATA, TLAST, TUSER and TVALID to the corresponding BD’s port.

  1. 4.png

     Validate the BD, you should get no error. Save the BD

Validate the IP in RTL simulation

  1. Launch the behavioral simulation and run it for 7ms

  2. The simulation will stop after 6.23ms with the following messages

 

Image written
Configured and output resolution match, test succeeded

 This looks promising as the output size is as expected

  1. We can start by looking at the image image_out_1.ppm created in /proj_1/proj_1.sim/sim_1/behav/xsim with GIMP

 

5.png

 

We can see that we get a nice pattern and that the image size is 320x480. In the test bench, the TPG was configured to output 640x480 thus everything looks correct.

  1. We can now have a final inspection by looking at the waveform

 6.png

 

We can see from the TDATA and TVALID output signals from the TPG and from the Video Crop that the video crop seems to correctly output only half of the image. Thus, everything looks also good.

We can notice that the IP keeps sending the tdata and tlast signals for the second half of the image. This is correct according to the AXI4-Stream specification. As tvalid is low, the other signals are not “transmitted” (thus they can take any value).

  1. Close the simulation and close Vivado

What Next?

 

  • Do you have issues/questions following this Vivado Beginner Series?
    1. Search on the Xilinx forums for similar questions
    2. Create a new topic on the HLS Board or Video Board for your issue/question with the title starting with [Video Beginner Series 18] and followed by a quick description of your issue/question

 

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Florent
Product Application Engineer - Xilinx Technical Support EMEA
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