UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Moderator
Moderator
6,251 Views
Registered: ‎11-09-2015

Video Beginner Series 2: From Native video to AXI4-Stream

Introduction

 

This Video Beginner Series 2 introduces the AXI4-Stream interface, how it is used in Xilinx All Programmable devices to carry video data and how to convert native video data to AXI4-Stream data.

 

 

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

 

Summary

 

1. AXI4-Stream for Xilinx Video IPs

2. Tutorial - From Native Video Data to AXI4-Stream

3. What Next?

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Tags (1)
3 Replies
Moderator
Moderator
6,249 Views
Registered: ‎11-09-2015

Video Beginner Series 2: From Native video to AXI4-Stream - AXI4-Stream for Xilinx Video IPs

AXI4-Stream for Xilinx Video IPs

 

AXI4-Stream is a protocol part of ARM AMBA4 and used for high-speed streaming data. The AXI4-Stream protocol defines a single channel for transmission of streaming data. The AXI4-Stream is used to connect one (or multiple) master(s) which transmits the data to one (or multiple) slave(s) which receives the data.

 

The Xilinx UG934 defines how the AXI4-Stream interface is used by Xilinx Video IPs to carry Video data. To work with Xilinx Video IPs, five signals are required:

 

  • tdata : carries the video data from the master to the slave
  • tvalid : signal sent by the master to indicate when the data on tdata is valid
  • tready : used by the slave to indicate when it is ready
  • tuser : used by Xilinx Video IPs to indicates the first pixel of a frame (from the master to the slave)
  • tlast : used by Xilinx Video IPs to indicates the last pixel of a line (from the master to the slave)

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
6,238 Views
Registered: ‎11-09-2015

Video Beginner Series 2: From Native video to AXI4-Stream - Tutorial

Tutorial - From Native Video Data to AXI4-Stream

 

 Note: This tutorial is intended to be used only with 2018.1 and in behavioral simulation only

 

Build the Vivado project

 

  1. Download the tutorial files and unzip the folder
  2. Open Vivado 2018.1
  3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0002)
  4. In the tcl console, source the script create_proj.tcl (source ./create_proj.tcl)

 

Understand the design

 

 5. In Vivado, in the source window, double click on the block design to open it

 6. You can then view the diagram of the design

 

 1.png

 

 7. The VGA_SOURCE IP (and the clocking wizard) is the same as in the Video Beginner Series 1

The Utility Logic Vector is used to synchronize the reset with the lock signal from the clocking wizard. The reset won’t be released while the clock is not locked and the input reset is not released.

The Video In to AXI4-Stream IP is a Xilinx IP used to convert Native Video Data to AXI4-Stream. Information for this IP can be found in the PG043.

The concat IP is used to create a single bus with the 3 color components (Red, Green, and Blue). They need to be mapped following the AXI4-Stream requirements. As per the PG043, the green component needs to be at the LSB, the red component at the MSB and the blue component in-between:

2.jpg

 

Understand the AXI4-Stream interface

 

 8. Launch the simulation for the design (Run Simulation > Run Behavioral Simulation)

 

 9. Run the simulation for 20ms

 

 10. Find the time when the Video In to AXI4S starts having data valid at its output ( rising edge m_axis_video_tvalid)

      Q1. Check the event before this rising edge. What event triggered the Video In to AXI4S to get valid data?

 3.jpg

 

 11. The signal wr_data_count_i is an internal signal of the Video In to AXI4S IP which indicates how many data words are ready (in the internal FIFO). Check this signal between simulation times 16663.374259us and 16663.874259us.

      Q2. What behavior do you see on the signal wr_data_count_i?
      Q3. What does it means for the output data?
      Q4. Check the signals m_axis_video_tvalid and m_axis_video_tready for during this simulation time and conclude what are the requirements for data transmission??

 

 12. Check the frequency of hsync_out and m_axis_video_tlast. You can see that both signals are happening at the same frequency as they both indicating the boundary of a line.

4.jpg

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
6,237 Views
Registered: ‎11-09-2015

Video Beginner Series 2: From Native video to AXI4-Stream - What Next?

What Next?

 

 

  • You liked this Video Series?
    • You can give Kudos using the Kudos button  kudos.PNG
    • Make sure you are following the Xilinx Video Series topic to be informed when an new topic is published (Go to the Xilinx Video Series topic > Options > Subscribe)
      subscribe.PNG

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**