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Video Beginner Series 4: Simulation with the Xilinx TPG IP

Introduction

 

 

This Video Beginner Series 4 shows how to use the Xilinx Video Test Pattern Generator (TPG) in simulation using the Xilinx Verification IP (VIP) to configure it.

TPG.JPG

 

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Summary

 

1. Xilinx Test Pattern Generator and AXI VIP IPs

2. Tutorial - Run a simulation with the TPG IP

3. What Next?

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Video Beginner Series 4: Simulation with the Xilinx TPG IP - Xilinx Test Pattern Generator and AXI VIP IPs

Xilinx Test Pattern Generator and AXI VIP IPs

 

 

The Xilinx Test Pattern Generator (TPG) IP can generate several video test patterns that are commonly used in the video industry for verification and testing.

 

The selection of the pattern, the size of the output video and many other settings can be configured by configuring the hardware registers using the AXI4-Lite interface of the TPG.

 

When running on a board, the TPG IP hardware registers are usually programmed using the TPG drivers on a processor like a Microblaze or a Zynq/Zynq MPSoC.

 

In simulation, you can simplify the design and program the TPG hardware registers using a Verification IP which would act as an AXI4-Lite master.

 

For information on the Test Pattern Generator, refer to its Product Guide (PG103).

 

Good to know: The Xilinx TPG is provided at no cost but requires a free license which can be generated from your Xilinx licensing account.

 

The AXI Verification IP (VIP) can be used to emulate a master/slave interface on three versions of the AXI protocol (AXI3, AXI4, and AXI4-Lite). It can also be used as protocol checker for these three version of the AXI Protocol.

 

Good to know: To enjoy all the features of the AXI VIP, it must be in a Verilog hierarchy.

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Video Beginner Series 4: Simulation with the Xilinx TPG IP - Tutorial - Run a simulation with the TPG IP

Tutorial - Run a simulation with the TPG IP

 

Note: This tutorial is intended to be used only with Vivado 2018.1 and only in simulation

 

Build the Vivado project

 

  1. Download the tutorial files and unzip the folder

  2. Open Vivado 2018.1

  3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0004)

  4. In the tcl console, source the script tcl (source ./create_proj.tcl)
    Note: A valid license for the Test Pattern Generator is required to build the design.

Understand the design

  1. In Vivado, in the source window, double click on the block design to open it

  2. You can then view the diagram of the design
    1.jpg

 

    1. The design only has an AXI VIP, configured as Master connected directly to the TPG IP, and used to configure the following TPG registers:
  • ACTIVE_HEIGHT (Address 0x0010) and ACTIVE_WIDTH (Address 0x0018)
    Set the size of the frame
    2.jpg
  •   BACKGROUND_PATTERN_IP (Address 0x0020)
    In this simulation, the value set for the background pattern ID is 9 which corresponds to a color bars pattern.
    3.jpg
  • CONTROL (Address 0x0000)
    Value 0x81 to start the TPG and keep it running after the first frame
    4.jpg

 

Launch the simulation

  1. Launch the behavioral simulation (Run Simulation > Run Behavioral Simulation)

  2. Run the simulation for 6 ms.

  3. The simulation will stop when the first frame will be completely outputted from the TPG IP. The test bench will check that the size of the frame outputted by the TPG correspond to what was configured.

Understand the simulation

  1. Go at the simulation time 250ns. You can see that the address 0x10 is set on the write address channel of the AXI4-Lite (s_axi_CTRL_AWADDR)
    5.jpg

Q1. What does this address correspond to?

Q2. From the simulation waveform and the signals on the AXI4-Lite interface, what will be the size of the frame (height and width) outputted by the TPG IP in this case?
Q3. Open the test bench file (tb_tpg.sv) and confirm the settings for the frame size.

 

  1. From simulation time 1.27us you can see the TPG outputting data on the AXI4-Stream Interface (m_axis_video_TVALID = ‘1’)
    6.jpg

Q4. What is the value of the first pixel (m_axis_video_TDATA)?

Q5. What will be the color of the first pixel knowing that the color space is RGB?

 

Good to know: For a more advance simulation for the TPG, use the example design for this IP. Refer to Chapter 6 of PG103 for information on generating the TPG example design.

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Video Beginner Series 4: Simulation with the Xilinx TPG IP - What Next?

What Next?

 

 

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**