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Registered: ‎11-09-2015

Video Beginner Series 5: Saving simulation outputs to an image file (PPM)

Introduction

 

 

This Video Beginner Series 5 shows how to output AXI4-Stream image data from simulation to an image file (PPM) using systemVerilog.

Note: Make sure to read the Video Beginner Series 3 before reading this Video Beginner Series 5.

 

 

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

 

Summary

 

1. Writing files in systemVerilog

2. Tutorial - Outputting an image file from Simulation
3. What next?

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Video Beginner Series 5: Saving simulation outputs to an image file - Writing files in systemVerilog

Writing files in systemVerilog

 

To open file in systemVerilog we can use the system task $fopen as in Verilog (refer to Xilinx Beginner Series 3).

When opened, we can write into a file using the system task $fwrite:

 

$fwrite (fd, format_string, arg);

This procedure has the following parameters:

  • fd: file descriptor
  • format_string : formatted string
  • arg : arguments for the formatted string

 

In this project, the data are written after the PPM header (refer to Xilinx Beginner Series 3).

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
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Registered: ‎11-09-2015

Video Beginner Series 5: Saving simulation outputs to an image file - Tutorial - Outputting an image file from Simulation

Tutorial - Outputting an image file from Simulation

 

Note: This tutorial is intended to be used only with Vivado 2018.1 and only in simulation

 

Build the Vivado project

 

  1. Download the tutorial files and unzip the folder

  2. Open Vivado 2018.1

  3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0005)

  4. In the tcl console, source the script tcl (source ./create_proj.tcl)

Note: A valid license for the Test Pattern Generator is required to build the design.

 

Launch the simulation

  1. Launch the behavioral simulation (Run Simulation > Run Behavioral Simulation)

  2. Run the simulation for 6 ms.

  3. The simulation will stop when the first frame will be completely outputted from the TPG IP. The test bench will check that the size of the frame outputted by the TPG correspond to what was configured.

  4. When the simulation is over, you should see the following messages in the TCL console:

 

Image written
Configured and output resolution match, test succeeded

 

 

It indicates that the PPM image file was created with the image data and that the simulation was successful.

 

  1. Find the image file ppm generated in XVES_0005/proj_1/proj_1.sim/ sim_1/behav/xsim and open it with GIMP (refer to the video series 3)

  2. You can see that the pattern generated by the TPG:

 13.png

This pattern is called “color bars”

 

Change the generated pattern

 

  1. Open the test bench file (Double click on tb_tpg.sv in the source window to open the file in the vivado text editor)

  2. Find the line corresponding to the TPG Background Pattern setting

 

//////////////////////////////////////////////////////////////////////////////////
// TPG configuration
// Selected Background pattern
// This Value should be between 0 and 19
integer pattern_id = 8'h09;

 

 

 

  1. Change the pattern_id value to 0x0B

 

integer pattern_id = 8'h0B;

 

 

  1. Run the simulation for 6 ms.

  2. Open the generate image using GIMP. You can see the now a Tartan Color Bar pattern

 2.png

 

  1. Try to change the value of pattern_id to get other patterns following the BACKGROUND_PATTERN_ID register from PG103

3.png

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎11-09-2015

Re: Video Beginner Series 5: Saving simulation outputs to an image file - Tutorial - Outputting an image file from Simulation

What Next?

 

 

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Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**